arm64: dts: imx8mm: Add imx8mm ddr4 evk board support

Add the board dts support for i.MX8MM DDR4 EVK board.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 296c84a..54b7a34 100644 (file)
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
 
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts
new file mode 100644 (file)
index 0000000..6c079c0
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8mm-evk.dtsi"
+
+/ {
+       model = "FSL i.MX8MM DDR4 EVK with CYW43455 WIFI/BT board";
+       compatible = "fsl,imx8mm-ddr4-evk", "fsl,imx8mm";
+
+       leds {
+               pinctrl-0 = <&pinctrl_gpio_led_2>;
+
+               status {
+                       gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
+               };
+       };
+};
+
+&gpmi {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_gpmi_nand>;
+       nand-on-flash-bbt;
+       status = "okay";
+};
+
+&iomuxc {
+       pinctrl_gpmi_nand: gpmi-nand {
+               fsl,pins = <
+                       MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE               0x00000096
+                       MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B           0x00000096
+                       MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B           0x00000096
+                       MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE               0x00000096
+                       MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00         0x00000096
+                       MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01         0x00000096
+                       MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02         0x00000096
+                       MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03         0x00000096
+                       MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04         0x00000096
+                       MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05         0x00000096
+                       MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06         0x00000096
+                       MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07         0x00000096
+                       MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B             0x00000096
+                       MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B       0x00000056
+                       MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B             0x00000096
+                       MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B             0x00000096
+               >;
+       };
+
+       pinctrl_gpio_led_2: gpioled2grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4       0x19
+               >;
+       };
+};