{cax.|add.} %3,%1,%2
{ai.|addic.} %3,%1,%2"
[(set_attr "type" "compare")])
-
+
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
(compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
{cax.|add.} %0,%1,%2
{ai.|addic.} %0,%1,%2"
[(set_attr "type" "compare")])
-
+
;; Split an add that we can't do in one insn into two insns, each of which
;; does one 16-bit part. This is used by combine. Note that the low-order
;; add should be last in case the result gets used in an address.
else
return \"{andil.|andi.} %4,%1,%3\";
}
-
+
if (start + size >= 32)
operands[3] = const0_rtx;
else
operands[3] = gen_rtx (CONST_INT, VOIDmode, (1 << (32 - start)) - 1);
return \"{andil.|andi.} %0,%1,%3\";
}
-
+
if (start + size >= 32)
operands[3] = const0_rtx;
else
""
"#"
[(set_attr "length" "8")])
-
+
(define_split
[(set (match_operand:DI 0 "gpc_reg_operand" "=")
(plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
(reg:SI 3))]
"TARGET_HARD_FLOAT"
"
-{
+{
rs6000_trunc_used = 1;
}")
"
{ operands[2] = operand_subword (operands[0], 0, 0, SFmode);
operands[3] = operand_subword (operands[1], 0, 0, SFmode); }")
-
+
(define_insn ""
[(set (match_operand:SF 0 "fp_reg_or_mem_operand" "=f,f,m")
(match_operand:SF 1 "input_operand" "f,m,f"))]
[(parallel [(set (match_operand:TI 0 "general_operand" "")
(match_operand:TI 1 "general_operand" ""))
(clobber (scratch:SI))])]
- "TARGET_MULTIPLE || TARGET_POWERPC64"
+ "TARGET_STRING || TARGET_POWERPC64"
"
{
if (GET_CODE (operands[0]) == MEM)
[(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
(match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
(clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
- "TARGET_MULTIPLE && TARGET_POWER && ! TARGET_POWERPC64
+ "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
&& (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
"*
{
[(set (match_operand:TI 0 "reg_or_mem_operand" "=m,????r,????r")
(match_operand:TI 1 "reg_or_mem_operand" "r,r,m"))
(clobber (match_scratch:SI 2 "=X,X,X"))]
- "TARGET_MULTIPLE && !TARGET_POWER && ! TARGET_POWERPC64
+ "TARGET_STRING && !TARGET_POWER && ! TARGET_POWERPC64
&& (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
"*
{
[(match_par_dup 3 [(set (match_operand:SI 0 "" "")
(match_operand:SI 1 "" ""))
(use (match_operand:SI 2 "" ""))])]
- "TARGET_MULTIPLE"
+ "TARGET_STRING"
"
{
int regno;
[(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 1 "gpc_reg_operand" "=r")
(match_operand:SI 2 "indirect_operand" "Q"))])]
- "TARGET_MULTIPLE"
+ "TARGET_STRING"
"*
{
/* We have to handle the case where the pseudo used to contain the address
(match_operand:SI 1 "" ""))
(clobber (scratch:SI))
(use (match_operand:SI 2 "" ""))])]
- "TARGET_MULTIPLE"
+ "TARGET_STRING"
"
{
int regno;
[(set (match_operand:SI 1 "indirect_operand" "=Q")
(match_operand:SI 2 "gpc_reg_operand" "r"))
(clobber (match_scratch:SI 3 "=q"))])]
- "TARGET_MULTIPLE && TARGET_POWER"
+ "TARGET_STRING && TARGET_POWER"
"{stsi|stswi} %2,%P1,%O0")
(define_insn ""
[(set (match_operand:SI 1 "indirect_operand" "=Q")
(match_operand:SI 2 "gpc_reg_operand" "r"))
(clobber (match_scratch:SI 3 "X"))])]
- "TARGET_MULTIPLE && !TARGET_POWER"
+ "TARGET_STRING && !TARGET_POWER"
"{stsi|stswi} %2,%P1,%O0")
+
+\f
+;; String/block move insn.
+;; Argument 0 is the destination
+;; Argument 1 is the source
+;; Argument 2 is the length
+;; Argument 3 is the alignment
+
+(define_expand "movstrsi"
+ [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
+ (match_operand:BLK 1 "memory_operand" ""))
+ (use (match_operand:SI 2 "general_operand" ""))
+ (use (match_operand:SI 3 "immediate_operand" ""))])]
+ ""
+ "
+{
+ if (expand_block_move (operands))
+ DONE;
+ else
+ FAIL;
+}")
+
+;; Move up to 32 bytes at a time. The fixed registers are needed because the
+;; register allocator doesn't have a clue about allocating 8 word registers
+(define_expand "movstrsi_8reg"
+ [(parallel [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
+ (mem:BLK (match_operand:SI 1 "register_operand" "")))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_operand:SI 4 "immediate_operand" "")))
+ (set (match_dup 1)
+ (plus:SI (match_dup 1)
+ (match_dup 4)))
+ (use (match_operand:SI 2 "immediate_operand" ""))
+ (use (match_operand:SI 3 "immediate_operand" ""))
+ (clobber (reg:SI 5))
+ (clobber (reg:SI 6))
+ (clobber (reg:SI 7))
+ (clobber (reg:SI 8))
+ (clobber (reg:SI 9))
+ (clobber (reg:SI 10))
+ (clobber (reg:SI 11))
+ (clobber (reg:SI 12))
+ (clobber (match_scratch:SI 5 ""))])]
+ "TARGET_STRING"
+ "")
+
+(define_insn ""
+ [(set (mem:BLK (match_operand:SI 0 "register_operand" "+&b,&b"))
+ (mem:BLK (match_operand:SI 1 "register_operand" "+&b,&b")))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_operand:SI 4 "immediate_operand" "O,i")))
+ (set (match_dup 1)
+ (plus:SI (match_dup 1)
+ (match_dup 4)))
+ (use (match_operand:SI 2 "immediate_operand" "i,i"))
+ (use (match_operand:SI 3 "immediate_operand" "i,i"))
+ (clobber (match_operand:SI 5 "register_operand" "r,r"))
+ (clobber (reg:SI 6))
+ (clobber (reg:SI 7))
+ (clobber (reg:SI 8))
+ (clobber (reg:SI 9))
+ (clobber (reg:SI 10))
+ (clobber (reg:SI 11))
+ (clobber (reg:SI 12))
+ (clobber (match_scratch:SI 6 "=q,q"))]
+ "TARGET_STRING && TARGET_POWER
+ && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) || INTVAL (operands[2]) == 0)
+ && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
+ && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
+ && REGNO (operands[5]) == 5"
+ "@
+ {lsi|lswi} %5,%1,%2\;{stsi|stswi} %5,%0,%2
+ {lsi|lswi} %5,%1,%2\;{cal %0,%4(%0)|addi %0,%0,%4}\;{stsi|stswi} %5,%0,%2\;{cal %1,%4(%1)|addi %1,%1,%4}"
+ [(set_attr "length" "8,16")])
+
+(define_insn ""
+ [(set (mem:BLK (match_operand:SI 0 "register_operand" "+&b,&b"))
+ (mem:BLK (match_operand:SI 1 "register_operand" "+&b,&b")))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_operand:SI 4 "immediate_operand" "O,i")))
+ (set (match_dup 1)
+ (plus:SI (match_dup 1)
+ (match_dup 4)))
+ (use (match_operand:SI 2 "immediate_operand" "i,i"))
+ (use (match_operand:SI 3 "immediate_operand" "i,i"))
+ (clobber (match_operand:SI 5 "register_operand" "r,r"))
+ (clobber (reg:SI 6))
+ (clobber (reg:SI 7))
+ (clobber (reg:SI 8))
+ (clobber (reg:SI 9))
+ (clobber (reg:SI 10))
+ (clobber (reg:SI 11))
+ (clobber (reg:SI 12))
+ (clobber (match_scratch:SI 6 "X,X"))]
+ "TARGET_STRING && !TARGET_POWER
+ && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) || INTVAL (operands[2]) == 0)
+ && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
+ && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
+ && REGNO (operands[5]) == 5"
+ "@
+ {lsi|lswi} %5,%1,%2\;{stsi|stswi} %5,%0,%2
+ {lsi|lswi} %5,%1,%2\;{cal %0,%4(%0)|addi %0,%0,%4}\;{stsi|stswi} %5,%0,%2\;{cal %1,%4(%1)|addi %1,%1,%4}"
+ [(set_attr "length" "8,16")])
+
+;; Move up to 24 bytes at a time. The fixed registers are needed because the
+;; register allocator doesn't have a clue about allocating 6 word registers
+(define_expand "movstrsi_6reg"
+ [(parallel [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
+ (mem:BLK (match_operand:SI 1 "register_operand" "")))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_operand:SI 4 "immediate_operand" "")))
+ (set (match_dup 1)
+ (plus:SI (match_dup 1)
+ (match_dup 4)))
+ (use (match_operand:SI 2 "immediate_operand" ""))
+ (use (match_operand:SI 3 "immediate_operand" ""))
+ (clobber (reg:SI 7))
+ (clobber (reg:SI 8))
+ (clobber (reg:SI 9))
+ (clobber (reg:SI 10))
+ (clobber (reg:SI 11))
+ (clobber (reg:SI 12))
+ (clobber (match_scratch:SI 5 ""))])]
+ "TARGET_STRING"
+ "")
+
+(define_insn ""
+ [(set (mem:BLK (match_operand:SI 0 "register_operand" "+&b,&b"))
+ (mem:BLK (match_operand:SI 1 "register_operand" "+&b,&b")))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_operand:SI 4 "immediate_operand" "O,i")))
+ (set (match_dup 1)
+ (plus:SI (match_dup 1)
+ (match_dup 4)))
+ (use (match_operand:SI 2 "immediate_operand" "i,i"))
+ (use (match_operand:SI 3 "immediate_operand" "i,i"))
+ (clobber (match_operand:SI 5 "register_operand" "r,r"))
+ (clobber (reg:SI 8))
+ (clobber (reg:SI 9))
+ (clobber (reg:SI 10))
+ (clobber (reg:SI 11))
+ (clobber (reg:SI 12))
+ (clobber (match_scratch:SI 6 "=q,q"))]
+ "TARGET_STRING && TARGET_POWER
+ && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
+ && (REGNO (operands[0]) < 7 || REGNO (operands[0]) > 12)
+ && (REGNO (operands[1]) < 7 || REGNO (operands[1]) > 12)
+ && REGNO (operands[5]) == 7"
+ "@
+ {lsi|lswi} %5,%1,%2\;{stsi|stswi} %5,%0,%2
+ {lsi|lswi} %5,%1,%2\;{cal %0,%4(%0)|addi %0,%0,%4}\;{stsi|stswi} %5,%0,%2\;{cal %1,%4(%1)|addi %1,%1,%4}"
+ [(set_attr "length" "8,16")])
+
+(define_insn ""
+ [(set (mem:BLK (match_operand:SI 0 "register_operand" "+&b,&b"))
+ (mem:BLK (match_operand:SI 1 "register_operand" "+&b,&b")))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_operand:SI 4 "immediate_operand" "O,i")))
+ (set (match_dup 1)
+ (plus:SI (match_dup 1)
+ (match_dup 4)))
+ (use (match_operand:SI 2 "immediate_operand" "i,i"))
+ (use (match_operand:SI 3 "immediate_operand" "i,i"))
+ (clobber (match_operand:SI 5 "register_operand" "r,r"))
+ (clobber (reg:SI 8))
+ (clobber (reg:SI 9))
+ (clobber (reg:SI 10))
+ (clobber (reg:SI 11))
+ (clobber (reg:SI 12))
+ (clobber (match_scratch:SI 6 "X,X"))]
+ "TARGET_STRING && !TARGET_POWER
+ && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
+ && (REGNO (operands[0]) < 7 || REGNO (operands[0]) > 12)
+ && (REGNO (operands[1]) < 7 || REGNO (operands[1]) > 12)
+ && REGNO (operands[5]) == 7"
+ "@
+ {lsi|lswi} %5,%1,%2\;{stsi|stswi} %5,%0,%2
+ {lsi|lswi} %5,%1,%2\;{cal %0,%4(%0)|addi %0,%0,%4}\;{stsi|stswi} %5,%0,%2\;{cal %1,%4(%1)|addi %1,%1,%4}"
+ [(set_attr "length" "8,16")])
+
+;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill problems
+;; with TImode
+(define_expand "movstrsi_4reg"
+ [(parallel [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
+ (mem:BLK (match_operand:SI 1 "register_operand" "")))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_operand:SI 4 "immediate_operand" "")))
+ (set (match_dup 1)
+ (plus:SI (match_dup 1)
+ (match_dup 4)))
+ (use (match_operand:SI 2 "immediate_operand" ""))
+ (use (match_operand:SI 3 "immediate_operand" ""))
+ (clobber (reg:SI 9))
+ (clobber (reg:SI 10))
+ (clobber (reg:SI 11))
+ (clobber (reg:SI 12))
+ (clobber (match_scratch:SI 5 ""))])]
+ "TARGET_STRING"
+ "")
+
+(define_insn ""
+ [(set (mem:BLK (match_operand:SI 0 "register_operand" "+&b,&b"))
+ (mem:BLK (match_operand:SI 1 "register_operand" "+&b,&b")))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_operand:SI 4 "immediate_operand" "O,i")))
+ (set (match_dup 1)
+ (plus:SI (match_dup 1)
+ (match_dup 4)))
+ (use (match_operand:SI 2 "immediate_operand" "i,i"))
+ (use (match_operand:SI 3 "immediate_operand" "i,i"))
+ (clobber (match_operand:SI 5 "register_operand" "r,r"))
+ (clobber (reg:SI 10))
+ (clobber (reg:SI 11))
+ (clobber (reg:SI 12))
+ (clobber (match_scratch:SI 6 "=q,q"))]
+ "TARGET_STRING && TARGET_POWER
+ && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
+ && (REGNO (operands[0]) < 9 || REGNO (operands[0]) > 12)
+ && (REGNO (operands[1]) < 9 || REGNO (operands[1]) > 12)
+ && REGNO (operands[5]) == 9"
+ "@
+ {lsi|lswi} %5,%1,%2\;{stsi|stswi} %5,%0,%2
+ {lsi|lswi} %5,%1,%2\;{cal %0,%4(%0)|addi %0,%0,%4}\;{stsi|stswi} %5,%0,%2\;{cal %1,%4(%1)|addi %1,%1,%4}"
+ [(set_attr "length" "8,16")])
+
+(define_insn ""
+ [(set (mem:BLK (match_operand:SI 0 "register_operand" "+&b,&b"))
+ (mem:BLK (match_operand:SI 1 "register_operand" "+&b,&b")))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_operand:SI 4 "immediate_operand" "O,i")))
+ (set (match_dup 1)
+ (plus:SI (match_dup 1)
+ (match_dup 4)))
+ (use (match_operand:SI 2 "immediate_operand" "i,i"))
+ (use (match_operand:SI 3 "immediate_operand" "i,i"))
+ (clobber (match_operand:SI 5 "register_operand" "r,r"))
+ (clobber (reg:SI 10))
+ (clobber (reg:SI 11))
+ (clobber (reg:SI 12))
+ (clobber (match_scratch:SI 6 "X,X"))]
+ "TARGET_STRING && !TARGET_POWER
+ && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
+ && (REGNO (operands[0]) < 9 || REGNO (operands[0]) > 12)
+ && (REGNO (operands[1]) < 9 || REGNO (operands[1]) > 12)
+ && REGNO (operands[5]) == 9"
+ "@
+ {lsi|lswi} %5,%1,%2\;{stsi|stswi} %5,%0,%2
+ {lsi|lswi} %5,%1,%2\;{cal %0,%4(%0)|addi %0,%0,%4}\;{stsi|stswi} %5,%0,%2\;{cal %1,%4(%1)|addi %1,%1,%4}"
+ [(set_attr "length" "8,16")])
+
+;; Move up to 8 bytes at a time.
+(define_expand "movstrsi_2reg"
+ [(parallel [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
+ (mem:BLK (match_operand:SI 1 "register_operand" "")))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_operand:SI 4 "immediate_operand" "")))
+ (set (match_dup 1)
+ (plus:SI (match_dup 1)
+ (match_dup 4)))
+ (use (match_operand:SI 2 "immediate_operand" ""))
+ (use (match_operand:SI 3 "immediate_operand" ""))
+ (clobber (match_scratch:DI 5 ""))
+ (clobber (match_scratch:SI 6 ""))])]
+ "TARGET_STRING && !TARGET_64BIT"
+ "")
+
+(define_insn ""
+ [(set (mem:BLK (match_operand:SI 0 "register_operand" "+&b,&b"))
+ (mem:BLK (match_operand:SI 1 "register_operand" "+&b,&b")))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_operand:SI 4 "immediate_operand" "O,i")))
+ (set (match_dup 1)
+ (plus:SI (match_dup 1)
+ (match_dup 4)))
+ (use (match_operand:SI 2 "immediate_operand" "i,i"))
+ (use (match_operand:SI 3 "immediate_operand" "i,i"))
+ (clobber (match_scratch:DI 5 "=&r,&r"))
+ (clobber (match_scratch:SI 6 "=q,q"))]
+ "TARGET_STRING && TARGET_POWER && !TARGET_64BIT
+ && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
+ "@
+ {lsi|lswi} %5,%1,%2\;{stsi|stswi} %5,%0,%2
+ {lsi|lswi} %5,%1,%2\;{cal %0,%4(%0)|addi %0,%0,%4}\;{stsi|stswi} %5,%0,%2\;{cal %1,%4(%1)|addi %1,%1,%4}"
+ [(set_attr "length" "8,16")])
+
+(define_insn ""
+ [(set (mem:BLK (match_operand:SI 0 "register_operand" "+&b,&b"))
+ (mem:BLK (match_operand:SI 1 "register_operand" "+&b,&b")))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_operand:SI 4 "immediate_operand" "O,i")))
+ (set (match_dup 1)
+ (plus:SI (match_dup 1)
+ (match_dup 4)))
+ (use (match_operand:SI 2 "immediate_operand" "i,i"))
+ (use (match_operand:SI 3 "immediate_operand" "i,i"))
+ (clobber (match_scratch:DI 5 "=&r,&r"))
+ (clobber (match_scratch:SI 6 "X,X"))]
+ "TARGET_STRING && !TARGET_POWER && !TARGET_64BIT
+ && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
+ "@
+ {lsi|lswi} %5,%1,%2\;{stsi|stswi} %5,%0,%2
+ {lsi|lswi} %5,%1,%2\;{cal %0,%4(%0)|addi %0,%0,%4}\;{stsi|stswi} %5,%0,%2\;{cal %1,%4(%1)|addi %1,%1,%4}"
+ [(set_attr "length" "8,16")])
+
+;; Move up to 4 bytes at a time.
+(define_expand "movstrsi_1reg"
+ [(parallel [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
+ (mem:BLK (match_operand:SI 1 "register_operand" "")))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_operand:SI 4 "immediate_operand" "")))
+ (set (match_dup 1)
+ (plus:SI (match_dup 1)
+ (match_dup 4)))
+ (use (match_operand:SI 2 "immediate_operand" ""))
+ (use (match_operand:SI 3 "immediate_operand" ""))
+ (clobber (match_scratch:SI 5 ""))
+ (clobber (match_scratch:SI 6 ""))])]
+ "TARGET_STRING"
+ "")
+
+(define_insn ""
+ [(set (mem:BLK (match_operand:SI 0 "register_operand" "+&b,&b"))
+ (mem:BLK (match_operand:SI 1 "register_operand" "+&b,&b")))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_operand:SI 4 "immediate_operand" "O,i")))
+ (set (match_dup 1)
+ (plus:SI (match_dup 1)
+ (match_dup 4)))
+ (use (match_operand:SI 2 "immediate_operand" "i,i"))
+ (use (match_operand:SI 3 "immediate_operand" "i,i"))
+ (clobber (match_scratch:SI 5 "=&r,&r"))
+ (clobber (match_scratch:SI 6 "=q,q"))]
+ "TARGET_STRING && TARGET_POWER
+ && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
+ "@
+ {lsi|lswi} %5,%1,%2\;{stsi|stswi} %5,%0,%2
+ {lsi|lswi} %5,%1,%2\;{cal %0,%4(%0)|addi %0,%0,%4}\;{stsi|stswi} %5,%0,%2\;{cal %1,%4(%1)|addi %1,%1,%4}"
+ [(set_attr "length" "8,16")])
+
+(define_insn ""
+ [(set (mem:BLK (match_operand:SI 0 "register_operand" "+&b,&b"))
+ (mem:BLK (match_operand:SI 1 "register_operand" "+&b,&b")))
+ (set (match_dup 0)
+ (plus:SI (match_dup 0)
+ (match_operand:SI 4 "immediate_operand" "O,i")))
+ (set (match_dup 1)
+ (plus:SI (match_dup 1)
+ (match_dup 4)))
+ (use (match_operand:SI 2 "immediate_operand" "i,i"))
+ (use (match_operand:SI 3 "immediate_operand" "i,i"))
+ (clobber (match_scratch:SI 5 "=&r,&r"))
+ (clobber (match_scratch:SI 6 "X,X"))]
+ "TARGET_STRING && !TARGET_POWER
+ && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
+ "@
+ {lsi|lswi} %5,%1,%2\;{stsi|stswi} %5,%0,%2
+ {lsi|lswi} %5,%1,%2\;{cal %0,%4(%0)|addi %0,%0,%4}\;{stsi|stswi} %5,%0,%2\;{cal %1,%4(%1)|addi %1,%1,%4}"
+ [(set_attr "length" "8,16")])
+
\f
-;; Define insns that do load or store with update. Some of these we can
+;; Define insns that do load or store with update. Some of these we can
;; get by using pre-decrement or pre-increment, but the hardware can also
;; do cases where the increment is not the size of the object.
;;
;; Next come insns related to the calling sequence.
;;
;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
-;; We move the back-chain and decrement the stack pointer.
+;; We move the back-chain and decrement the stack pointer.
(define_expand "allocate_stack"
[(set (reg:SI 1)
emit_move_insn (operand_subword (operands[0], 1, 0, DImode), operands[1]);
DONE;
}")
-
+
(define_expand "restore_stack_nonlocal"
[(match_operand:SI 0 "register_operand" "")
(match_operand:DI 1 "memory_operand" "")]
;; A function pointer is a pointer to a data area whose first word contains
;; the actual address of the function, whose second word contains a pointer
;; to its TOC, and whose third word contains a value to place in the static
-;; chain register (r11). Note that if we load the static chain, our
+;; chain register (r11). Note that if we load the static chain, our
;; "trampoline" need not have any executable code.
;;
;; operands[0] is an SImode pseudo in which we place the address of the
"")
\f
;; Compare insns are next. Note that the RS/6000 has two types of compares,
-;; signed & unsigned, and one type of branch.
+;; signed & unsigned, and one type of branch.
;;
;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
;; insns, and branches. We store the operands of compares until we see
""
"#"
[(set_attr "length" "8")])
-
+
(define_insn ""
[(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
(compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
""
"#"
[(set_attr "length" "8")])
-
+
(define_split
[(set (match_operand:CC 3 "cc_reg_operand" "")
(compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
(define_insn ""
[(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x")
- (compare:CC
+ (compare:CC
(eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
(const_int 0)))
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x")
- (compare:CC
+ (compare:CC
(plus:SI
(eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
(define_insn ""
[(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x")
- (compare:CC
+ (compare:CC
(plus:SI
(eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
""
"{cror 0,0,0|nop}")
\f
-;; Define the subtract-one-and-jump insns, starting with the template
+;; Define the subtract-one-and-jump insns, starting with the template
;; so loop.c knows what to generate.
(define_expand "decrement_and_branchsi"
;; We need to be able to do this for any operand, including MEM, or we
;; will cause reload to blow up since we don't allow output reloads on
-;; JUMP_INSNs.
+;; JUMP_INSNs.
(define_insn ""
[(set (pc)
(if_then_else (ne (match_operand:SI 1 "register_operand" "0,*r,*r")
}"
[(set_attr "type" "branch")
(set_attr "length" "*,12,16")])
-
+
;; Similar, but we can use GE since we have a REG_NONNEG.
(define_insn ""
[(set (pc)
}"
[(set_attr "type" "branch")
(set_attr "length" "*,12,16")])
-
+
(define_insn ""
[(set (pc)
(if_then_else (eq (match_operand:SI 1 "register_operand" "0,*r,*r")