return MRST_OK;
}
-
-#if 0
-/*
- * save_display_registers
- *
- * Description: We are going to suspend so save current display
- * register state.
- */
-static void save_display_registers(struct drm_device *dev)
-{
- struct drm_psb_private *dev_priv = dev->dev_private;
- int i;
-
- /* Display arbitration control + watermarks */
- dev_priv->saveDSPARB = PSB_RVDC32(DSPARB);
- dev_priv->saveDSPFW1 = PSB_RVDC32(DSPFW1);
- dev_priv->saveDSPFW2 = PSB_RVDC32(DSPFW2);
- dev_priv->saveDSPFW3 = PSB_RVDC32(DSPFW3);
- dev_priv->saveDSPFW4 = PSB_RVDC32(DSPFW4);
- dev_priv->saveDSPFW5 = PSB_RVDC32(DSPFW5);
- dev_priv->saveDSPFW6 = PSB_RVDC32(DSPFW6);
- dev_priv->saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT);
-
- /* Pipe & plane A info */
- dev_priv->savePIPEACONF = PSB_RVDC32(PIPEACONF);
- dev_priv->savePIPEASRC = PSB_RVDC32(PIPEASRC);
- dev_priv->saveFPA0 = PSB_RVDC32(MRST_FPA0);
- dev_priv->saveFPA1 = PSB_RVDC32(MRST_FPA1);
- dev_priv->saveDPLL_A = PSB_RVDC32(MRST_DPLL_A);
- dev_priv->saveHTOTAL_A = PSB_RVDC32(HTOTAL_A);
- dev_priv->saveHBLANK_A = PSB_RVDC32(HBLANK_A);
- dev_priv->saveHSYNC_A = PSB_RVDC32(HSYNC_A);
- dev_priv->saveVTOTAL_A = PSB_RVDC32(VTOTAL_A);
- dev_priv->saveVBLANK_A = PSB_RVDC32(VBLANK_A);
- dev_priv->saveVSYNC_A = PSB_RVDC32(VSYNC_A);
- dev_priv->saveBCLRPAT_A = PSB_RVDC32(BCLRPAT_A);
- dev_priv->saveDSPACNTR = PSB_RVDC32(DSPACNTR);
- dev_priv->saveDSPASTRIDE = PSB_RVDC32(DSPASTRIDE);
- dev_priv->saveDSPAADDR = PSB_RVDC32(DSPABASE);
- dev_priv->saveDSPASURF = PSB_RVDC32(DSPASURF);
- dev_priv->saveDSPALINOFF = PSB_RVDC32(DSPALINOFF);
- dev_priv->saveDSPATILEOFF = PSB_RVDC32(DSPATILEOFF);
-
- /*save cursor regs*/
- dev_priv->saveDSPACURSOR_CTRL = PSB_RVDC32(CURACNTR);
- dev_priv->saveDSPACURSOR_BASE = PSB_RVDC32(CURABASE);
- dev_priv->saveDSPACURSOR_POS = PSB_RVDC32(CURAPOS);
-
- /*save palette (gamma) */
- for (i = 0; i < 256; i++)
- dev_priv->save_palette_a[i] = PSB_RVDC32(PALETTE_A + (i<<2));
-
- /*save performance state*/
- dev_priv->savePERF_MODE = PSB_RVDC32(MRST_PERF_MODE);
-
- /* LVDS state */
- dev_priv->savePP_CONTROL = PSB_RVDC32(PP_CONTROL);
- dev_priv->savePFIT_PGM_RATIOS = PSB_RVDC32(PFIT_PGM_RATIOS);
- dev_priv->savePFIT_AUTO_RATIOS = PSB_RVDC32(PFIT_AUTO_RATIOS);
- dev_priv->saveBLC_PWM_CTL = PSB_RVDC32(BLC_PWM_CTL);
- dev_priv->saveBLC_PWM_CTL2 = PSB_RVDC32(BLC_PWM_CTL2);
- dev_priv->saveLVDS = PSB_RVDC32(LVDS);
- dev_priv->savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL);
- dev_priv->savePP_ON_DELAYS = PSB_RVDC32(LVDSPP_ON);
- dev_priv->savePP_OFF_DELAYS = PSB_RVDC32(LVDSPP_OFF);
- dev_priv->savePP_DIVISOR = PSB_RVDC32(PP_CYCLE);
-
- /* HW overlay */
- dev_priv->saveOV_OVADD = PSB_RVDC32(OV_OVADD);
- dev_priv->saveOV_OGAMC0 = PSB_RVDC32(OV_OGAMC0);
- dev_priv->saveOV_OGAMC1 = PSB_RVDC32(OV_OGAMC1);
- dev_priv->saveOV_OGAMC2 = PSB_RVDC32(OV_OGAMC2);
- dev_priv->saveOV_OGAMC3 = PSB_RVDC32(OV_OGAMC3);
- dev_priv->saveOV_OGAMC4 = PSB_RVDC32(OV_OGAMC4);
- dev_priv->saveOV_OGAMC5 = PSB_RVDC32(OV_OGAMC5);
-
- /* MIPI DSI */
- dev_priv->saveMIPI = PSB_RVDC32(MIPI);
- dev_priv->saveDEVICE_READY_REG = PSB_RVDC32(DEVICE_READY_REG);
- dev_priv->saveINTR_EN_REG = PSB_RVDC32(INTR_EN_REG);
- dev_priv->saveDSI_FUNC_PRG_REG = PSB_RVDC32(DSI_FUNC_PRG_REG);
- dev_priv->saveHS_TX_TIMEOUT_REG = PSB_RVDC32(HS_TX_TIMEOUT_REG);
- dev_priv->saveLP_RX_TIMEOUT_REG = PSB_RVDC32(LP_RX_TIMEOUT_REG);
- dev_priv->saveTURN_AROUND_TIMEOUT_REG =
- PSB_RVDC32(TURN_AROUND_TIMEOUT_REG);
- dev_priv->saveDEVICE_RESET_REG = PSB_RVDC32(DEVICE_RESET_REG);
- dev_priv->saveDPI_RESOLUTION_REG =
- PSB_RVDC32(DPI_RESOLUTION_REG);
- dev_priv->saveHORIZ_SYNC_PAD_COUNT_REG =
- PSB_RVDC32(HORIZ_SYNC_PAD_COUNT_REG);
- dev_priv->saveHORIZ_BACK_PORCH_COUNT_REG =
- PSB_RVDC32(HORIZ_BACK_PORCH_COUNT_REG);
- dev_priv->saveHORIZ_FRONT_PORCH_COUNT_REG =
- PSB_RVDC32(HORIZ_FRONT_PORCH_COUNT_REG);
- dev_priv->saveHORIZ_ACTIVE_AREA_COUNT_REG =
- PSB_RVDC32(HORIZ_ACTIVE_AREA_COUNT_REG);
- dev_priv->saveVERT_SYNC_PAD_COUNT_REG =
- PSB_RVDC32(VERT_SYNC_PAD_COUNT_REG);
- dev_priv->saveVERT_BACK_PORCH_COUNT_REG =
- PSB_RVDC32(VERT_BACK_PORCH_COUNT_REG);
- dev_priv->saveVERT_FRONT_PORCH_COUNT_REG =
- PSB_RVDC32(VERT_FRONT_PORCH_COUNT_REG);
- dev_priv->saveHIGH_LOW_SWITCH_COUNT_REG =
- PSB_RVDC32(HIGH_LOW_SWITCH_COUNT_REG);
- dev_priv->saveINIT_COUNT_REG = PSB_RVDC32(INIT_COUNT_REG);
- dev_priv->saveMAX_RET_PAK_REG = PSB_RVDC32(MAX_RET_PAK_REG);
- dev_priv->saveVIDEO_FMT_REG = PSB_RVDC32(VIDEO_FMT_REG);
- dev_priv->saveEOT_DISABLE_REG = PSB_RVDC32(EOT_DISABLE_REG);
- dev_priv->saveLP_BYTECLK_REG = PSB_RVDC32(LP_BYTECLK_REG);
- dev_priv->saveHS_LS_DBI_ENABLE_REG =
- PSB_RVDC32(HS_LS_DBI_ENABLE_REG);
- dev_priv->saveTXCLKESC_REG = PSB_RVDC32(TXCLKESC_REG);
- dev_priv->saveDPHY_PARAM_REG = PSB_RVDC32(DPHY_PARAM_REG);
- dev_priv->saveMIPI_CONTROL_REG = PSB_RVDC32(MIPI_CONTROL_REG);
-
- /* DPST registers */
- dev_priv->saveHISTOGRAM_INT_CONTROL_REG = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
- dev_priv->saveHISTOGRAM_LOGIC_CONTROL_REG = PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
-}
-
-
-/*
- * restore_display_registers
- *
- * Description: We are going to resume so restore display register state.
- */
-static void restore_display_registers(struct drm_device *dev)
-{
- struct drm_psb_private *dev_priv = dev->dev_private;
- unsigned long i, pp_stat;
-
- /* Display arbitration + watermarks */
- PSB_WVDC32(dev_priv->saveDSPARB, DSPARB);
- PSB_WVDC32(dev_priv->saveDSPFW1, DSPFW1);
- PSB_WVDC32(dev_priv->saveDSPFW2, DSPFW2);
- PSB_WVDC32(dev_priv->saveDSPFW3, DSPFW3);
- PSB_WVDC32(dev_priv->saveDSPFW4, DSPFW4);
- PSB_WVDC32(dev_priv->saveDSPFW5, DSPFW5);
- PSB_WVDC32(dev_priv->saveDSPFW6, DSPFW6);
- PSB_WVDC32(dev_priv->saveCHICKENBIT, DSPCHICKENBIT);
-
- /*make sure VGA plane is off. it initializes to on after reset!*/
- PSB_WVDC32(0x80000000, VGACNTRL);
-
- /* set the plls */
- PSB_WVDC32(dev_priv->saveFPA0, MRST_FPA0);
- PSB_WVDC32(dev_priv->saveFPA1, MRST_FPA1);
- /* Actually enable it */
- PSB_WVDC32(dev_priv->saveDPLL_A, MRST_DPLL_A);
- DRM_UDELAY(150);
-
- /* Restore mode */
- PSB_WVDC32(dev_priv->saveHTOTAL_A, HTOTAL_A);
- PSB_WVDC32(dev_priv->saveHBLANK_A, HBLANK_A);
- PSB_WVDC32(dev_priv->saveHSYNC_A, HSYNC_A);
- PSB_WVDC32(dev_priv->saveVTOTAL_A, VTOTAL_A);
- PSB_WVDC32(dev_priv->saveVBLANK_A, VBLANK_A);
- PSB_WVDC32(dev_priv->saveVSYNC_A, VSYNC_A);
- PSB_WVDC32(dev_priv->savePIPEASRC, PIPEASRC);
- PSB_WVDC32(dev_priv->saveBCLRPAT_A, BCLRPAT_A);
-
- /*restore performance mode*/
- PSB_WVDC32(dev_priv->savePERF_MODE, MRST_PERF_MODE);
-
- /*enable the pipe*/
- if (dev_priv->iLVDS_enable)
- PSB_WVDC32(dev_priv->savePIPEACONF, PIPEACONF);
-
- /* set up MIPI */
- PSB_WVDC32(dev_priv->saveINTR_EN_REG, INTR_EN_REG);
- PSB_WVDC32(dev_priv->saveDSI_FUNC_PRG_REG, DSI_FUNC_PRG_REG);
- PSB_WVDC32(dev_priv->saveHS_TX_TIMEOUT_REG, HS_TX_TIMEOUT_REG);
- PSB_WVDC32(dev_priv->saveLP_RX_TIMEOUT_REG, LP_RX_TIMEOUT_REG);
- PSB_WVDC32(dev_priv->saveTURN_AROUND_TIMEOUT_REG,
- TURN_AROUND_TIMEOUT_REG);
- PSB_WVDC32(dev_priv->saveDEVICE_RESET_REG, DEVICE_RESET_REG);
- PSB_WVDC32(dev_priv->saveDPI_RESOLUTION_REG,
- DPI_RESOLUTION_REG);
- PSB_WVDC32(dev_priv->saveHORIZ_SYNC_PAD_COUNT_REG,
- HORIZ_SYNC_PAD_COUNT_REG);
- PSB_WVDC32(dev_priv->saveHORIZ_BACK_PORCH_COUNT_REG,
- HORIZ_BACK_PORCH_COUNT_REG);
- PSB_WVDC32(dev_priv->saveHORIZ_FRONT_PORCH_COUNT_REG,
- HORIZ_FRONT_PORCH_COUNT_REG);
- PSB_WVDC32(dev_priv->saveHORIZ_ACTIVE_AREA_COUNT_REG,
- HORIZ_ACTIVE_AREA_COUNT_REG);
- PSB_WVDC32(dev_priv->saveVERT_SYNC_PAD_COUNT_REG,
- VERT_SYNC_PAD_COUNT_REG);
- PSB_WVDC32(dev_priv->saveVERT_BACK_PORCH_COUNT_REG,
- VERT_BACK_PORCH_COUNT_REG);
- PSB_WVDC32(dev_priv->saveVERT_FRONT_PORCH_COUNT_REG,
- VERT_FRONT_PORCH_COUNT_REG);
- PSB_WVDC32(dev_priv->saveHIGH_LOW_SWITCH_COUNT_REG,
- HIGH_LOW_SWITCH_COUNT_REG);
- PSB_WVDC32(dev_priv->saveINIT_COUNT_REG, INIT_COUNT_REG);
- PSB_WVDC32(dev_priv->saveMAX_RET_PAK_REG, MAX_RET_PAK_REG);
- PSB_WVDC32(dev_priv->saveVIDEO_FMT_REG, VIDEO_FMT_REG);
- PSB_WVDC32(dev_priv->saveEOT_DISABLE_REG, EOT_DISABLE_REG);
- PSB_WVDC32(dev_priv->saveLP_BYTECLK_REG, LP_BYTECLK_REG);
- PSB_WVDC32(dev_priv->saveHS_LS_DBI_ENABLE_REG,
- HS_LS_DBI_ENABLE_REG);
- PSB_WVDC32(dev_priv->saveTXCLKESC_REG, TXCLKESC_REG);
- PSB_WVDC32(dev_priv->saveDPHY_PARAM_REG, DPHY_PARAM_REG);
- PSB_WVDC32(dev_priv->saveMIPI_CONTROL_REG, MIPI_CONTROL_REG);
-
- /*set up the plane*/
- PSB_WVDC32(dev_priv->saveDSPALINOFF, DSPALINOFF);
- PSB_WVDC32(dev_priv->saveDSPASTRIDE, DSPASTRIDE);
- PSB_WVDC32(dev_priv->saveDSPATILEOFF, DSPATILEOFF);
-
- /* Enable the plane */
- PSB_WVDC32(dev_priv->saveDSPACNTR, DSPACNTR);
- PSB_WVDC32(dev_priv->saveDSPASURF, DSPASURF);
-
- /*Enable Cursor A*/
- PSB_WVDC32(dev_priv->saveDSPACURSOR_CTRL, CURACNTR);
- PSB_WVDC32(dev_priv->saveDSPACURSOR_POS, CURAPOS);
- PSB_WVDC32(dev_priv->saveDSPACURSOR_BASE, CURABASE);
-
- /* restore palette (gamma) */
- /*DRM_UDELAY(50000); */
- for (i = 0; i < 256; i++)
- PSB_WVDC32(dev_priv->save_palette_a[i], PALETTE_A + (i<<2));
-
- if (dev_priv->iLVDS_enable) {
- PSB_WVDC32(dev_priv->saveBLC_PWM_CTL2, BLC_PWM_CTL2);
- PSB_WVDC32(dev_priv->saveLVDS, LVDS); /*port 61180h*/
- PSB_WVDC32(dev_priv->savePFIT_CONTROL, PFIT_CONTROL);
- PSB_WVDC32(dev_priv->savePFIT_PGM_RATIOS, PFIT_PGM_RATIOS);
- PSB_WVDC32(dev_priv->savePFIT_AUTO_RATIOS, PFIT_AUTO_RATIOS);
- PSB_WVDC32(dev_priv->saveBLC_PWM_CTL, BLC_PWM_CTL);
- PSB_WVDC32(dev_priv->savePP_ON_DELAYS, LVDSPP_ON);
- PSB_WVDC32(dev_priv->savePP_OFF_DELAYS, LVDSPP_OFF);
- PSB_WVDC32(dev_priv->savePP_DIVISOR, PP_CYCLE);
- PSB_WVDC32(dev_priv->savePP_CONTROL, PP_CONTROL);
- } else { /* enable MIPI */
- PSB_WVDC32(MIPI_PORT_EN | MIPI_BORDER_EN, MIPI); /*force on port*/
- PSB_WVDC32(1, DEVICE_READY_REG);/* force on to re-program */
- dev_priv->init_drvIC(dev);
- PSB_WVDC32(dev_priv->saveMIPI, MIPI); /*port 61190h*/
- PSB_WVDC32(dev_priv->saveDEVICE_READY_REG, DEVICE_READY_REG);
- if (dev_priv->saveDEVICE_READY_REG)
- PSB_WVDC32(DPI_TURN_ON, DPI_CONTROL_REG);
- PSB_WVDC32(dev_priv->savePIPEACONF, PIPEACONF);
- PSB_WVDC32(dev_priv->saveBLC_PWM_CTL2, BLC_PWM_CTL2);
- PSB_WVDC32(dev_priv->saveBLC_PWM_CTL, BLC_PWM_CTL);
- }
-
- /*wait for cycle delay*/
- do {
- pp_stat = PSB_RVDC32(PP_STATUS);
- } while (pp_stat & 0x08000000);
-
- DRM_UDELAY(999);
- /*wait for panel power up*/
- do {
- pp_stat = PSB_RVDC32(PP_STATUS);
- } while (pp_stat & 0x10000000);
-
- /* restore HW overlay */
- PSB_WVDC32(dev_priv->saveOV_OVADD, OV_OVADD);
- PSB_WVDC32(dev_priv->saveOV_OGAMC0, OV_OGAMC0);
- PSB_WVDC32(dev_priv->saveOV_OGAMC1, OV_OGAMC1);
- PSB_WVDC32(dev_priv->saveOV_OGAMC2, OV_OGAMC2);
- PSB_WVDC32(dev_priv->saveOV_OGAMC3, OV_OGAMC3);
- PSB_WVDC32(dev_priv->saveOV_OGAMC4, OV_OGAMC4);
- PSB_WVDC32(dev_priv->saveOV_OGAMC5, OV_OGAMC5);
-
- /* DPST registers */
- PSB_WVDC32(dev_priv->saveHISTOGRAM_INT_CONTROL_REG, HISTOGRAM_INT_CONTROL);
- PSB_WVDC32(dev_priv->saveHISTOGRAM_LOGIC_CONTROL_REG, HISTOGRAM_LOGIC_CONTROL);
-}
-
-
-PVRSRV_ERROR MRSTLFBPrePowerState(IMG_HANDLE hDevHandle,
- PVRSRV_DEV_POWER_STATE eNewPowerState,
- PVRSRV_DEV_POWER_STATE eCurrentPowerState)
-{
- MRSTLFB_DEVINFO* psDevInfo = (MRSTLFB_DEVINFO *)hDevHandle;
- struct drm_device* dev = psDevInfo->psDrmDevice;
- struct drm_psb_private *dev_priv = dev->dev_private;
- int pp_stat;
-
- if ((eNewPowerState == eCurrentPowerState) ||
- (eNewPowerState == PVRSRV_DEV_POWER_STATE_ON))
- return PVRSRV_OK;
-
- if (!dev_priv->iLVDS_enable && dev_priv->dsi_prePowerState != NULL)
- dev_priv->dsi_prePowerState(dev);
-
- save_display_registers(dev);
-
- if (dev_priv->iLVDS_enable) {
- /*shutdown the panel*/
- PSB_WVDC32(0, PP_CONTROL);
-
- do {
- pp_stat = PSB_RVDC32(PP_STATUS);
- } while (pp_stat & 0x80000000);
-
- /*turn off the plane*/
- PSB_WVDC32(0x58000000, DSPACNTR);
- PSB_WVDC32(0, DSPASURF);/*trigger the plane disable*/
- msleep(4);
-
- /*turn off pipe*/
- PSB_WVDC32(0x0, PIPEACONF);
- msleep(8);
-
- /*turn off PLLs*/
- PSB_WVDC32(0, MRST_DPLL_A);
- }
-
- return PVRSRV_OK;
-}
-
-
-PVRSRV_ERROR MRSTLFBPostPowerState(IMG_HANDLE hDevHandle,
- PVRSRV_DEV_POWER_STATE eNewPowerState,
- PVRSRV_DEV_POWER_STATE eCurrentPowerState)
-{
- MRSTLFB_DEVINFO* psDevInfo = (MRSTLFB_DEVINFO *)hDevHandle;
- struct drm_device* dev = psDevInfo->psDrmDevice;
- struct drm_psb_private *dev_priv = dev->dev_private;
- struct psb_gtt *pg = dev_priv->pg;
-
- if ((eNewPowerState == eCurrentPowerState) ||
- (eNewPowerState == PVRSRV_DEV_POWER_STATE_OFF))
- return PVRSRV_OK;
-
- PSB_WVDC32(pg->pge_ctl | _PSB_PGETBL_ENABLED, PSB_PGETBL_CTL);
- pci_write_config_word(dev->pdev, PSB_GMCH_CTRL,
- pg->gmch_ctrl | _PSB_GMCH_ENABLED);
-
- /* Don't reinitialize the GTT as it is unnecessary. The gtt is
- * stored in memory so it will automatically be restored. All
- * we need to do is restore the PGETBL_CTL which we already do
- * above.
- */
- /*psb_gtt_init(dev_priv->pg, 1);*/
-
- restore_display_registers(dev);
-
- if (!dev_priv->iLVDS_enable && dev_priv->dsi_postPowerState != NULL)
- dev_priv->dsi_postPowerState(dev);
-
- return PVRSRV_OK;
-}
-#endif
projects / kernel / kernel-mfld-blackbay.git / commitdiff