clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKS

The way hw_onecell_data is declared:
  struct clk_hw_onecell_data {
          unsigned int num;
          struct clk_hw *hws[];
  };

makes it impossible to have the clk_hw table declared outside while
using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible
array member.

Completely move out of hw_onecell_data and add a custom
devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw
from the meson_aoclk_data struct to finally get rid on the
NR_CLKS define.

[jbrunet: Fixed whitespace checkpatch warning]
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-3-38172d17c27a@linaro.org
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index 5bf901d..caadaf9 100644 (file)
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -36,6 +36,7 @@ config COMMON_CLK_MESON_CLKC_UTILS
 config COMMON_CLK_MESON_AO_CLKC
        tristate
        select COMMON_CLK_MESON_REGMAP
+       select COMMON_CLK_MESON_CLKC_UTILS
        select RESET_CONTROLLER
 
 config COMMON_CLK_MESON_EE_CLKC

diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c
index af6db43..53993d9 100644 (file)
--- a/drivers/clk/meson/axg-aoclk.c
+++ b/drivers/clk/meson/axg-aoclk.c
@@ -288,27 +288,24 @@ static struct clk_regmap *axg_aoclk_regmap[] = {
        &axg_aoclk_saradc_gate,
 };
 
-static const struct clk_hw_onecell_data axg_aoclk_onecell_data = {
-       .hws = {
-               [CLKID_AO_REMOTE]       = &axg_aoclk_remote.hw,
-               [CLKID_AO_I2C_MASTER]   = &axg_aoclk_i2c_master.hw,
-               [CLKID_AO_I2C_SLAVE]    = &axg_aoclk_i2c_slave.hw,
-               [CLKID_AO_UART1]        = &axg_aoclk_uart1.hw,
-               [CLKID_AO_UART2]        = &axg_aoclk_uart2.hw,
-               [CLKID_AO_IR_BLASTER]   = &axg_aoclk_ir_blaster.hw,
-               [CLKID_AO_SAR_ADC]      = &axg_aoclk_saradc.hw,
-               [CLKID_AO_CLK81]        = &axg_aoclk_clk81.hw,
-               [CLKID_AO_SAR_ADC_SEL]  = &axg_aoclk_saradc_mux.hw,
-               [CLKID_AO_SAR_ADC_DIV]  = &axg_aoclk_saradc_div.hw,
-               [CLKID_AO_SAR_ADC_CLK]  = &axg_aoclk_saradc_gate.hw,
-               [CLKID_AO_CTS_OSCIN]    = &axg_aoclk_cts_oscin.hw,
-               [CLKID_AO_32K_PRE]      = &axg_aoclk_32k_pre.hw,
-               [CLKID_AO_32K_DIV]      = &axg_aoclk_32k_div.hw,
-               [CLKID_AO_32K_SEL]      = &axg_aoclk_32k_sel.hw,
-               [CLKID_AO_32K]          = &axg_aoclk_32k.hw,
-               [CLKID_AO_CTS_RTC_OSCIN] = &axg_aoclk_cts_rtc_oscin.hw,
-       },
-       .num = NR_CLKS,
+static struct clk_hw *axg_aoclk_hw_clks[] = {
+       [CLKID_AO_REMOTE]       = &axg_aoclk_remote.hw,
+       [CLKID_AO_I2C_MASTER]   = &axg_aoclk_i2c_master.hw,
+       [CLKID_AO_I2C_SLAVE]    = &axg_aoclk_i2c_slave.hw,
+       [CLKID_AO_UART1]        = &axg_aoclk_uart1.hw,
+       [CLKID_AO_UART2]        = &axg_aoclk_uart2.hw,
+       [CLKID_AO_IR_BLASTER]   = &axg_aoclk_ir_blaster.hw,
+       [CLKID_AO_SAR_ADC]      = &axg_aoclk_saradc.hw,
+       [CLKID_AO_CLK81]        = &axg_aoclk_clk81.hw,
+       [CLKID_AO_SAR_ADC_SEL]  = &axg_aoclk_saradc_mux.hw,
+       [CLKID_AO_SAR_ADC_DIV]  = &axg_aoclk_saradc_div.hw,
+       [CLKID_AO_SAR_ADC_CLK]  = &axg_aoclk_saradc_gate.hw,
+       [CLKID_AO_CTS_OSCIN]    = &axg_aoclk_cts_oscin.hw,
+       [CLKID_AO_32K_PRE]      = &axg_aoclk_32k_pre.hw,
+       [CLKID_AO_32K_DIV]      = &axg_aoclk_32k_div.hw,
+       [CLKID_AO_32K_SEL]      = &axg_aoclk_32k_sel.hw,
+       [CLKID_AO_32K]          = &axg_aoclk_32k.hw,
+       [CLKID_AO_CTS_RTC_OSCIN] = &axg_aoclk_cts_rtc_oscin.hw,
 };
 
 static const struct meson_aoclk_data axg_aoclkc_data = {
@@ -317,7 +314,10 @@ static const struct meson_aoclk_data axg_aoclkc_data = {
        .reset          = axg_aoclk_reset,
        .num_clks       = ARRAY_SIZE(axg_aoclk_regmap),
        .clks           = axg_aoclk_regmap,
-       .hw_data        = &axg_aoclk_onecell_data,
+       .hw_clks        = {
+               .hws    = axg_aoclk_hw_clks,
+               .num    = ARRAY_SIZE(axg_aoclk_hw_clks),
+       },
 };
 
 static const struct of_device_id axg_aoclkc_match_table[] = {

diff --git a/drivers/clk/meson/axg-aoclk.h b/drivers/clk/meson/axg-aoclk.h
index 3cc27e8..fe23dc5 100644 (file)
--- a/drivers/clk/meson/axg-aoclk.h
+++ b/drivers/clk/meson/axg-aoclk.h
@@ -10,8 +10,6 @@
 #ifndef __AXG_AOCLKC_H
 #define __AXG_AOCLKC_H
 
-#define NR_CLKS        17
-
 #include <dt-bindings/clock/axg-aoclkc.h>
 #include <dt-bindings/reset/axg-aoclkc.h>
 

diff --git a/drivers/clk/meson/g12a-aoclk.c b/drivers/clk/meson/g12a-aoclk.c
index b52990e..6542094 100644 (file)
--- a/drivers/clk/meson/g12a-aoclk.c
+++ b/drivers/clk/meson/g12a-aoclk.c
@@ -411,39 +411,36 @@ static struct clk_regmap *g12a_aoclk_regmap[] = {
        &g12a_aoclk_saradc_gate,
 };
 
-static const struct clk_hw_onecell_data g12a_aoclk_onecell_data = {
-       .hws = {
-               [CLKID_AO_AHB]          = &g12a_aoclk_ahb.hw,
-               [CLKID_AO_IR_IN]        = &g12a_aoclk_ir_in.hw,
-               [CLKID_AO_I2C_M0]       = &g12a_aoclk_i2c_m0.hw,
-               [CLKID_AO_I2C_S0]       = &g12a_aoclk_i2c_s0.hw,
-               [CLKID_AO_UART]         = &g12a_aoclk_uart.hw,
-               [CLKID_AO_PROD_I2C]     = &g12a_aoclk_prod_i2c.hw,
-               [CLKID_AO_UART2]        = &g12a_aoclk_uart2.hw,
-               [CLKID_AO_IR_OUT]       = &g12a_aoclk_ir_out.hw,
-               [CLKID_AO_SAR_ADC]      = &g12a_aoclk_saradc.hw,
-               [CLKID_AO_MAILBOX]      = &g12a_aoclk_mailbox.hw,
-               [CLKID_AO_M3]           = &g12a_aoclk_m3.hw,
-               [CLKID_AO_AHB_SRAM]     = &g12a_aoclk_ahb_sram.hw,
-               [CLKID_AO_RTI]          = &g12a_aoclk_rti.hw,
-               [CLKID_AO_M4_FCLK]      = &g12a_aoclk_m4_fclk.hw,
-               [CLKID_AO_M4_HCLK]      = &g12a_aoclk_m4_hclk.hw,
-               [CLKID_AO_CLK81]        = &g12a_aoclk_clk81.hw,
-               [CLKID_AO_SAR_ADC_SEL]  = &g12a_aoclk_saradc_mux.hw,
-               [CLKID_AO_SAR_ADC_DIV]  = &g12a_aoclk_saradc_div.hw,
-               [CLKID_AO_SAR_ADC_CLK]  = &g12a_aoclk_saradc_gate.hw,
-               [CLKID_AO_CTS_OSCIN]    = &g12a_aoclk_cts_oscin.hw,
-               [CLKID_AO_32K_PRE]      = &g12a_aoclk_32k_by_oscin_pre.hw,
-               [CLKID_AO_32K_DIV]      = &g12a_aoclk_32k_by_oscin_div.hw,
-               [CLKID_AO_32K_SEL]      = &g12a_aoclk_32k_by_oscin_sel.hw,
-               [CLKID_AO_32K]          = &g12a_aoclk_32k_by_oscin.hw,
-               [CLKID_AO_CEC_PRE]      = &g12a_aoclk_cec_pre.hw,
-               [CLKID_AO_CEC_DIV]      = &g12a_aoclk_cec_div.hw,
-               [CLKID_AO_CEC_SEL]      = &g12a_aoclk_cec_sel.hw,
-               [CLKID_AO_CEC]          = &g12a_aoclk_cec.hw,
-               [CLKID_AO_CTS_RTC_OSCIN] = &g12a_aoclk_cts_rtc_oscin.hw,
-       },
-       .num = NR_CLKS,
+static struct clk_hw *g12a_aoclk_hw_clks[] = {
+       [CLKID_AO_AHB]          = &g12a_aoclk_ahb.hw,
+       [CLKID_AO_IR_IN]        = &g12a_aoclk_ir_in.hw,
+       [CLKID_AO_I2C_M0]       = &g12a_aoclk_i2c_m0.hw,
+       [CLKID_AO_I2C_S0]       = &g12a_aoclk_i2c_s0.hw,
+       [CLKID_AO_UART]         = &g12a_aoclk_uart.hw,
+       [CLKID_AO_PROD_I2C]     = &g12a_aoclk_prod_i2c.hw,
+       [CLKID_AO_UART2]        = &g12a_aoclk_uart2.hw,
+       [CLKID_AO_IR_OUT]       = &g12a_aoclk_ir_out.hw,
+       [CLKID_AO_SAR_ADC]      = &g12a_aoclk_saradc.hw,
+       [CLKID_AO_MAILBOX]      = &g12a_aoclk_mailbox.hw,
+       [CLKID_AO_M3]           = &g12a_aoclk_m3.hw,
+       [CLKID_AO_AHB_SRAM]     = &g12a_aoclk_ahb_sram.hw,
+       [CLKID_AO_RTI]          = &g12a_aoclk_rti.hw,
+       [CLKID_AO_M4_FCLK]      = &g12a_aoclk_m4_fclk.hw,
+       [CLKID_AO_M4_HCLK]      = &g12a_aoclk_m4_hclk.hw,
+       [CLKID_AO_CLK81]        = &g12a_aoclk_clk81.hw,
+       [CLKID_AO_SAR_ADC_SEL]  = &g12a_aoclk_saradc_mux.hw,
+       [CLKID_AO_SAR_ADC_DIV]  = &g12a_aoclk_saradc_div.hw,
+       [CLKID_AO_SAR_ADC_CLK]  = &g12a_aoclk_saradc_gate.hw,
+       [CLKID_AO_CTS_OSCIN]    = &g12a_aoclk_cts_oscin.hw,
+       [CLKID_AO_32K_PRE]      = &g12a_aoclk_32k_by_oscin_pre.hw,
+       [CLKID_AO_32K_DIV]      = &g12a_aoclk_32k_by_oscin_div.hw,
+       [CLKID_AO_32K_SEL]      = &g12a_aoclk_32k_by_oscin_sel.hw,
+       [CLKID_AO_32K]          = &g12a_aoclk_32k_by_oscin.hw,
+       [CLKID_AO_CEC_PRE]      = &g12a_aoclk_cec_pre.hw,
+       [CLKID_AO_CEC_DIV]      = &g12a_aoclk_cec_div.hw,
+       [CLKID_AO_CEC_SEL]      = &g12a_aoclk_cec_sel.hw,
+       [CLKID_AO_CEC]          = &g12a_aoclk_cec.hw,
+       [CLKID_AO_CTS_RTC_OSCIN] = &g12a_aoclk_cts_rtc_oscin.hw,
 };
 
 static const struct meson_aoclk_data g12a_aoclkc_data = {
@@ -452,7 +449,10 @@ static const struct meson_aoclk_data g12a_aoclkc_data = {
        .reset          = g12a_aoclk_reset,
        .num_clks       = ARRAY_SIZE(g12a_aoclk_regmap),
        .clks           = g12a_aoclk_regmap,
-       .hw_data        = &g12a_aoclk_onecell_data,
+       .hw_clks        = {
+               .hws    = g12a_aoclk_hw_clks,
+               .num    = ARRAY_SIZE(g12a_aoclk_hw_clks),
+       },
 };
 
 static const struct of_device_id g12a_aoclkc_match_table[] = {

diff --git a/drivers/clk/meson/g12a-aoclk.h b/drivers/clk/meson/g12a-aoclk.h
index a67c8a7..077bd25 100644 (file)
--- a/drivers/clk/meson/g12a-aoclk.h
+++ b/drivers/clk/meson/g12a-aoclk.h
@@ -24,8 +24,6 @@
 #define CLKID_AO_CEC_DIV       25
 #define CLKID_AO_CEC_SEL       26
 
-#define NR_CLKS        29
-
 #include <dt-bindings/clock/g12a-aoclkc.h>
 #include <dt-bindings/reset/g12a-aoclkc.h>
 

diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
index fce95cf..d2cf941 100644 (file)
--- a/drivers/clk/meson/gxbb-aoclk.c
+++ b/drivers/clk/meson/gxbb-aoclk.c
@@ -252,8 +252,7 @@ static struct clk_regmap *gxbb_aoclk[] = {
        &ao_cts_cec,
 };
 
-static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
-       .hws = {
+static struct clk_hw *gxbb_aoclk_hw_clks[] = {
                [CLKID_AO_REMOTE] = &remote_ao.hw,
                [CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw,
                [CLKID_AO_I2C_SLAVE] = &i2c_slave_ao.hw,
@@ -268,8 +267,6 @@ static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
                [CLKID_AO_32K] = &ao_32k.hw,
                [CLKID_AO_CTS_RTC_OSCIN] = &ao_cts_rtc_oscin.hw,
                [CLKID_AO_CLK81] = &ao_clk81.hw,
-       },
-       .num = NR_CLKS,
 };
 
 static const struct meson_aoclk_data gxbb_aoclkc_data = {
@@ -278,7 +275,10 @@ static const struct meson_aoclk_data gxbb_aoclkc_data = {
        .reset          = gxbb_aoclk_reset,
        .num_clks       = ARRAY_SIZE(gxbb_aoclk),
        .clks           = gxbb_aoclk,
-       .hw_data        = &gxbb_aoclk_onecell_data,
+       .hw_clks        = {
+               .hws    = gxbb_aoclk_hw_clks,
+               .num    = ARRAY_SIZE(gxbb_aoclk_hw_clks),
+       },
 };
 
 static const struct of_device_id gxbb_aoclkc_match_table[] = {

diff --git a/drivers/clk/meson/gxbb-aoclk.h b/drivers/clk/meson/gxbb-aoclk.h
index 1db16f9..94197b9 100644 (file)
--- a/drivers/clk/meson/gxbb-aoclk.h
+++ b/drivers/clk/meson/gxbb-aoclk.h
@@ -7,8 +7,6 @@
 #ifndef __GXBB_AOCLKC_H
 #define __GXBB_AOCLKC_H
 
-#define NR_CLKS        14
-
 #include <dt-bindings/clock/gxbb-aoclkc.h>
 #include <dt-bindings/reset/gxbb-aoclkc.h>
 

diff --git a/drivers/clk/meson/meson-aoclk.c b/drivers/clk/meson/meson-aoclk.c
index 434cd8f..e7a72bd 100644 (file)
--- a/drivers/clk/meson/meson-aoclk.c
+++ b/drivers/clk/meson/meson-aoclk.c
@@ -75,19 +75,18 @@ int meson_aoclkc_probe(struct platform_device *pdev)
                data->clks[clkid]->map = regmap;
 
        /* Register all clks */
-       for (clkid = 0; clkid < data->hw_data->num; clkid++) {
-               if (!data->hw_data->hws[clkid])
+       for (clkid = 0; clkid < data->hw_clks.num; clkid++) {
+               if (!data->hw_clks.hws[clkid])
                        continue;
 
-               ret = devm_clk_hw_register(dev, data->hw_data->hws[clkid]);
+               ret = devm_clk_hw_register(dev, data->hw_clks.hws[clkid]);
                if (ret) {
                        dev_err(dev, "Clock registration failed\n");
                        return ret;
                }
        }
 
-       return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
-               (void *) data->hw_data);
+       return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks);
 }
 EXPORT_SYMBOL_GPL(meson_aoclkc_probe);
 MODULE_LICENSE("GPL v2");

diff --git a/drivers/clk/meson/meson-aoclk.h b/drivers/clk/meson/meson-aoclk.h
index 605b438..308be3e 100644 (file)
--- a/drivers/clk/meson/meson-aoclk.h
+++ b/drivers/clk/meson/meson-aoclk.h
@@ -17,6 +17,7 @@
 #include <linux/reset-controller.h>
 
 #include "clk-regmap.h"
+#include "meson-clkc-utils.h"
 
 struct meson_aoclk_data {
        const unsigned int                      reset_reg;
@@ -24,7 +25,7 @@ struct meson_aoclk_data {
        const unsigned int                      *reset;
        const int                               num_clks;
        struct clk_regmap                       **clks;
-       const struct clk_hw_onecell_data        *hw_data;
+       struct meson_clk_hw_data                hw_clks;
 };
 
 struct meson_aoclk_reset_controller {