%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> zeroinitializer
ret <4 x i32> %2
}
+
+define <4 x i32> @rot_v4i32_allsignbits(<4 x i32> %x, <4 x i32> %y) {
+; XOP-LABEL: rot_v4i32_allsignbits:
+; XOP: # %bb.0:
+; XOP-NEXT: vpsrad $31, %xmm0, %xmm0
+; XOP-NEXT: vprotd %xmm1, %xmm0, %xmm0
+; XOP-NEXT: retq
+;
+; AVX512-LABEL: rot_v4i32_allsignbits:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpsrad $31, %xmm0, %xmm0
+; AVX512-NEXT: vprolvd %xmm1, %xmm0, %xmm0
+; AVX512-NEXT: retq
+ %1 = ashr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
+ %2 = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %1, <4 x i32> %1, <4 x i32> %y)
+ ret <4 x i32> %2
+}
+
declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)