amd: Hide amdgpu_drm.h on Windows

Declare missing definitions instead.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9708>

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 9fce76e..b1b950d 100644 (file)
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -26,7 +26,6 @@
 #include "ac_gpu_info.h"
 
 #include "addrlib/src/amdgpu_asic_addr.h"
-#include "drm-uapi/amdgpu_drm.h"
 #include "sid.h"
 #include "util/macros.h"
 #include "util/u_cpu_detect.h"
@@ -35,6 +34,51 @@
 #include <stdio.h>
 
 #ifdef _WIN32
+#define DRM_CAP_SYNCOBJ 0x13
+#define DRM_CAP_SYNCOBJ_TIMELINE 0x14
+#define AMDGPU_GEM_DOMAIN_GTT 0x2
+#define AMDGPU_GEM_DOMAIN_VRAM 0x4
+#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
+#define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10)
+#define AMDGPU_HW_IP_GFX 0
+#define AMDGPU_HW_IP_COMPUTE 1
+#define AMDGPU_HW_IP_DMA 2
+#define AMDGPU_HW_IP_UVD 3
+#define AMDGPU_HW_IP_VCE 4
+#define AMDGPU_HW_IP_UVD_ENC 5
+#define AMDGPU_HW_IP_VCN_DEC 6
+#define AMDGPU_HW_IP_VCN_ENC 7
+#define AMDGPU_HW_IP_VCN_JPEG 8
+#define AMDGPU_IDS_FLAGS_FUSION 0x1
+#define AMDGPU_IDS_FLAGS_PREEMPTION 0x2
+#define AMDGPU_IDS_FLAGS_TMZ 0x4
+#define AMDGPU_INFO_FW_VCE 0x1
+#define AMDGPU_INFO_FW_UVD 0x2
+#define AMDGPU_INFO_FW_GFX_ME 0x04
+#define AMDGPU_INFO_FW_GFX_PFP 0x05
+#define AMDGPU_INFO_FW_GFX_CE 0x06
+#define AMDGPU_INFO_DEV_INFO 0x16
+#define AMDGPU_INFO_MEMORY 0x19
+#define AMDGPU_INFO_VIDEO_CAPS_DECODE 0
+#define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1
+struct drm_amdgpu_heap_info {
+   uint64_t total_heap_size;
+};
+struct drm_amdgpu_memory_info {
+   struct drm_amdgpu_heap_info vram;
+   struct drm_amdgpu_heap_info cpu_accessible_vram;
+   struct drm_amdgpu_heap_info gtt;
+};
+struct drm_amdgpu_info_device {
+   uint32_t num_tcc_blocks;
+   uint32_t pa_sc_tile_steering_override;
+   uint64_t tcc_disabled_mask;
+};
+struct drm_amdgpu_info_hw_ip {
+   uint32_t ib_start_alignment;
+   uint32_t ib_size_alignment;
+   uint32_t available_rings;
+};
 typedef struct _drmPciBusInfo {
    uint16_t domain;
    uint8_t bus;
@@ -165,6 +209,7 @@ const char *amdgpu_get_marketing_name(amdgpu_device_handle dev)
    return NULL;
 }
 #else
+#include "drm-uapi/amdgpu_drm.h"
 #include <amdgpu.h>
 #include <xf86drm.h>
 #endif

diff --git a/src/amd/common/ac_rgp.c b/src/amd/common/ac_rgp.c
index 961b5d3..abd98fa 100644 (file)
--- a/src/amd/common/ac_rgp.c
+++ b/src/amd/common/ac_rgp.c
@@ -31,7 +31,21 @@
 
 #include "ac_sqtt.h"
 #include "ac_gpu_info.h"
+#ifdef _WIN32
+#define AMDGPU_VRAM_TYPE_UNKNOWN 0
+#define AMDGPU_VRAM_TYPE_GDDR1 1
+#define AMDGPU_VRAM_TYPE_DDR2  2
+#define AMDGPU_VRAM_TYPE_GDDR3 3
+#define AMDGPU_VRAM_TYPE_GDDR4 4
+#define AMDGPU_VRAM_TYPE_GDDR5 5
+#define AMDGPU_VRAM_TYPE_HBM   6
+#define AMDGPU_VRAM_TYPE_DDR3  7
+#define AMDGPU_VRAM_TYPE_DDR4  8
+#define AMDGPU_VRAM_TYPE_GDDR6 9
+#define AMDGPU_VRAM_TYPE_DDR5  10
+#else
 #include "drm-uapi/amdgpu_drm.h"
+#endif
 
 #include <stdbool.h>
 #include <string.h>

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 55519b6..0e7d907 100644 (file)
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -31,7 +31,6 @@
 #include "addrlib/inc/addrinterface.h"
 #include "addrlib/src/amdgpu_asic_addr.h"
 #include "amd_family.h"
-#include "drm-uapi/amdgpu_drm.h"
 #include "drm-uapi/drm_fourcc.h"
 #include "sid.h"
 #include "util/hash_table.h"
@@ -46,6 +45,43 @@
 #include <stdio.h>
 #include <stdlib.h>
 
+#ifdef _WIN32
+#define AMDGPU_TILING_ARRAY_MODE_SHIFT                 0
+#define AMDGPU_TILING_ARRAY_MODE_MASK                  0xf
+#define AMDGPU_TILING_PIPE_CONFIG_SHIFT                        4
+#define AMDGPU_TILING_PIPE_CONFIG_MASK                 0x1f
+#define AMDGPU_TILING_TILE_SPLIT_SHIFT                 9
+#define AMDGPU_TILING_TILE_SPLIT_MASK                  0x7
+#define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT            12
+#define AMDGPU_TILING_MICRO_TILE_MODE_MASK             0x7
+#define AMDGPU_TILING_BANK_WIDTH_SHIFT                 15
+#define AMDGPU_TILING_BANK_WIDTH_MASK                  0x3
+#define AMDGPU_TILING_BANK_HEIGHT_SHIFT                        17
+#define AMDGPU_TILING_BANK_HEIGHT_MASK                 0x3
+#define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT          19
+#define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK           0x3
+#define AMDGPU_TILING_NUM_BANKS_SHIFT                  21
+#define AMDGPU_TILING_NUM_BANKS_MASK                   0x3
+#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT               0
+#define AMDGPU_TILING_SWIZZLE_MODE_MASK                        0x1f
+#define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT            5
+#define AMDGPU_TILING_DCC_OFFSET_256B_MASK             0xFFFFFF
+#define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT              29
+#define AMDGPU_TILING_DCC_PITCH_MAX_MASK               0x3FFF
+#define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT                43
+#define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK         0x1
+#define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT       44
+#define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK                0x1
+#define AMDGPU_TILING_SCANOUT_SHIFT                    63
+#define AMDGPU_TILING_SCANOUT_MASK                     0x1
+#define AMDGPU_TILING_SET(field, value) \
+       (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
+#define AMDGPU_TILING_GET(value, field) \
+       (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
+#else
+#include "drm-uapi/amdgpu_drm.h"
+#endif
+
 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
 #endif