Removed MI_FLUSH and replaced them by proper pipe control

diff --git a/kernels/fft_kernels.cl b/kernels/fft_kernels.cl
index 5fe3d92..d226e76 100644 (file)
--- a/kernels/fft_kernels.cl
+++ b/kernels/fft_kernels.cl
@@ -10,8 +10,8 @@ k_sincos(int i, float *cretp)
        i -= 1024;
 
     float x = i * -ANGLE;
-    *cretp = native_cos(x);
-    return native_sin(x);
+    *cretp = cos(x);
+    return sin(x);
 }
 
 __attribute__((always_inline)) float4
@@ -19,8 +19,8 @@ k_sincos4(int4 i, float4 *cretp)
 {
     i -= (i > 512) & 1024;
     float4 x = convert_float4(i) * -ANGLE;
-    *cretp = native_cos(x);
-    return native_sin(x);
+    *cretp = cos(x);
+    return sin(x);
 }
 
 // Twiddle factor stuff

diff --git a/kernels/urng_output.bmp b/kernels/urng_output.bmp
index 42b1718..c004fa5 100644 (file)
Binary files a/kernels/urng_output.bmp and b/kernels/urng_output.bmp differ

diff --git a/src/cl_command_queue_gen6.c b/src/cl_command_queue_gen6.c
index e581a30..7858369 100644 (file)
--- a/src/cl_command_queue_gen6.c
+++ b/src/cl_command_queue_gen6.c
@@ -180,7 +180,7 @@ cl_command_queue_ND_range_gen6(cl_command_queue queue,
   /* Start a new batch buffer */
   gpgpu_batch_reset(gpgpu, batch_sz);
   gpgpu_batch_start(gpgpu);
-
+#if 1
   /* Push all media objects. We implement three paths to make it (a bit) faster.
    * Local IDs are shared from work group to work group. We allocate once the
    * buffers and reuse them
@@ -201,7 +201,7 @@ cl_command_queue_ND_range_gen6(cl_command_queue queue,
     cl_command_queue_enqueue_wk_grp(queue, ids, &header, thread_n, barrierID);
     barrierID = (barrierID + 1) % 16;
   }
-
+#endif
   gpgpu_batch_end(gpgpu, 0);
   gpgpu_flush(gpgpu);
 

diff --git a/src/intel/intel_gpgpu.c b/src/intel/intel_gpgpu.c
index 566051c..bf97223 100644 (file)
--- a/src/intel/intel_gpgpu.c
+++ b/src/intel/intel_gpgpu.c
@@ -499,6 +499,75 @@ static const uint32_t Gen7L3CacheConfigReg3DataTable[] =
 #define L3_CNTL_REG2_ADDRESS_OFFSET         ( 0xB020 )
 #define L3_CNTL_REG3_ADDRESS_OFFSET         ( 0xB024 )
 
+#define sizeof32(X) (sizeof(X) / sizeof(uint32_t))
+
+enum INSTRUCTION_PIPELINE
+{
+    PIPE_COMMON       = 0x0,
+    PIPE_SINGLE_DWORD = 0x1,
+    PIPE_COMMON_CTG   = 0x1,
+    PIPE_MEDIA        = 0x2,
+    PIPE_3D           = 0x3
+};
+
+enum GFX_OPCODE
+{
+    GFXOP_PIPELINED     = 0x0,
+    GFXOP_NONPIPELINED  = 0x1,
+    GFXOP_3DPRIMITIVE   = 0x3
+};
+
+enum INSTRUCTION_TYPE
+{
+    INSTRUCTION_MI      = 0x0,
+    INSTRUCTION_TRUSTED = 0x1,
+    INSTRUCTION_2D      = 0x2,
+    INSTRUCTION_GFX     = 0x3
+};
+
+enum GFX3DCONTROL_SUBOPCODE
+{
+    GFX3DSUBOP_3DCONTROL    = 0x00
+};
+
+enum GFX3D_OPCODE
+{
+    GFX3DOP_3DSTATE_PIPELINED       = 0x0,
+    GFX3DOP_3DSTATE_NONPIPELINED    = 0x1,
+    GFX3DOP_3DCONTROL               = 0x2,
+    GFX3DOP_3DPRIMITIVE             = 0x3
+};
+
+enum GFX3DSTATE_PIPELINED_SUBOPCODE
+{
+    GFX3DSUBOP_3DSTATE_PIPELINED_POINTERS       = 0x00,
+    GFX3DSUBOP_3DSTATE_BINDING_TABLE_POINTERS   = 0x01,
+    GFX3DSUBOP_3DSTATE_STATE_POINTER_INVALIDATE = 0x02,
+    GFX3DSUBOP_3DSTATE_VERTEX_BUFFERS           = 0x08,
+    GFX3DSUBOP_3DSTATE_VERTEX_ELEMENTS          = 0x09,
+    GFX3DSUBOP_3DSTATE_INDEX_BUFFER             = 0x0A,
+    GFX3DSUBOP_3DSTATE_VF_STATISTICS            = 0x0B,
+    GFX3DSUBOP_3DSTATE_CC_STATE_POINTERS        = 0x0E
+};
+
+static void
+gpgpu_pipe_control(intel_gpgpu_t *state)
+{
+  BEGIN_BATCH(state->batch, sizeof(i965_pipe_control_t) / sizeof(uint32_t));
+  i965_pipe_control_t* pc = (i965_pipe_control_t*)
+    intel_batchbuffer_alloc_space(state->batch, 0);
+  memset(pc, 0, sizeof(*pc));
+  pc->dw0.length = sizeof32(i965_pipe_control_t) - 2;
+  pc->dw0.instruction_subopcode = GFX3DSUBOP_3DCONTROL;
+  pc->dw0.instruction_opcode = GFX3DOP_3DCONTROL;
+  pc->dw0.instruction_pipeline = PIPE_3D;
+  pc->dw0.instruction_type = INSTRUCTION_GFX;
+  pc->dw1.render_target_cache_flush_enable = 1;
+  pc->dw1.cs_stall = 1;
+  pc->dw1.dc_flush_enable = 1;
+  ADVANCE_BATCH(state->batch);
+}
+
 LOCAL void
 intel_gpgpu_set_L3(intel_gpgpu_t *state, uint32_t use_barrier)
 {
@@ -518,14 +587,14 @@ intel_gpgpu_set_L3(intel_gpgpu_t *state, uint32_t use_barrier)
     OUT_BATCH(state->batch, Gen7L3CacheConfigReg3DataTable[4]);
   ADVANCE_BATCH(state->batch);
 
-  intel_batchbuffer_emit_mi_flush(state->batch);
+  gpgpu_pipe_control(state);
 }
 
 LOCAL void
 gpgpu_batch_start(intel_gpgpu_t *state)
 {
   intel_batchbuffer_start_atomic(state->batch, 256);
-  intel_batchbuffer_emit_mi_flush(state->batch);
+  gpgpu_pipe_control(state);
   if (state->drv->gen_ver >= 7)
     intel_gpgpu_set_L3(state, state->ker->use_barrier);
   gpgpu_select_pipeline(state);
@@ -567,11 +636,7 @@ gpgpu_batch_end(intel_gpgpu_t *state, int32_t flush_mode)
     ADVANCE_BATCH(state->batch);
   }
 
-  if(flush_mode) {
-    BEGIN_BATCH(state->batch, 1);
-    OUT_BATCH(state->batch, MI_FLUSH);
-    ADVANCE_BATCH(state->batch);
-  }
+  if(flush_mode) gpgpu_pipe_control(state);
   intel_batchbuffer_end_atomic(state->batch);
 }
 
@@ -948,7 +1013,7 @@ gpgpu_build_idrt(intel_gpgpu_t *state,
   for (i = 0; i < ker_n; i++) {
     memset(desc, 0, sizeof(*desc));
     desc->desc0.kernel_start_pointer = kernel[i].bo->offset >> 6; /* reloc */
-    desc->desc1.floating_point_mode = 1;
+    /* desc->desc1.floating_point_mode = 1; */
     /* desc->desc1 = 0; - no exception control, no SPF */
     /* desc->desc2 = 0; - no samplers */
     desc->desc2.sampler_state_pointer = state->sampler_state_b.bo->offset >> 5;

diff --git a/src/intel/intel_structs.h b/src/intel/intel_structs.h
index b82d770..7b873dd 100644 (file)
--- a/src/intel/intel_structs.h
+++ b/src/intel/intel_structs.h
@@ -20,274 +20,276 @@
 #ifndef __GENX_STRUCTS_H__
 #define __GENX_STRUCTS_H__
 
+#include <stdint.h>
+
 struct i965_vfe_state 
 {
   struct {
-    unsigned int per_thread_scratch_space:4;
-    unsigned int pad3:3;
-    unsigned int extend_vfe_state_present:1;
-    unsigned int pad2:2;
-    unsigned int scratch_base:22;
+    uint32_t per_thread_scratch_space:4;
+    uint32_t pad3:3;
+    uint32_t extend_vfe_state_present:1;
+    uint32_t pad2:2;
+    uint32_t scratch_base:22;
   } vfe0;
 
   struct {
-    unsigned int debug_counter_control:2;
-    unsigned int children_present:1;
-    unsigned int vfe_mode:4;
-    unsigned int pad2:2;
-    unsigned int num_urb_entries:7;
-    unsigned int urb_entry_alloc_size:9;
-    unsigned int max_threads:7;
+    uint32_t debug_counter_control:2;
+    uint32_t children_present:1;
+    uint32_t vfe_mode:4;
+    uint32_t pad2:2;
+    uint32_t num_urb_entries:7;
+    uint32_t urb_entry_alloc_size:9;
+    uint32_t max_threads:7;
   } vfe1;
 
   struct {
-    unsigned int pad4:4;
-    unsigned int interface_descriptor_base:28;
+    uint32_t pad4:4;
+    uint32_t interface_descriptor_base:28;
   } vfe2;
 };
 
 struct i965_vfe_state_ex 
 {
   struct {
-    unsigned int pad:8;
-    unsigned int obj_id:24;
+    uint32_t pad:8;
+    uint32_t obj_id:24;
   } vfex0;
 
   struct {
-    unsigned int residual_grf_offset:5;
-    unsigned int pad0:3;
-    unsigned int weight_grf_offset:5;
-    unsigned int pad1:3;
-    unsigned int residual_data_offset:8;
-    unsigned int sub_field_present_flag:2;
-    unsigned int residual_data_fix_offset:1;
-    unsigned int pad2:5;
+    uint32_t residual_grf_offset:5;
+    uint32_t pad0:3;
+    uint32_t weight_grf_offset:5;
+    uint32_t pad1:3;
+    uint32_t residual_data_offset:8;
+    uint32_t sub_field_present_flag:2;
+    uint32_t residual_data_fix_offset:1;
+    uint32_t pad2:5;
   }vfex1;
 
   struct {
-    unsigned int remap_index_0:4;
-    unsigned int remap_index_1:4;
-    unsigned int remap_index_2:4;
-    unsigned int remap_index_3:4;
-    unsigned int remap_index_4:4;
-    unsigned int remap_index_5:4;
-    unsigned int remap_index_6:4;
-    unsigned int remap_index_7:4;
+    uint32_t remap_index_0:4;
+    uint32_t remap_index_1:4;
+    uint32_t remap_index_2:4;
+    uint32_t remap_index_3:4;
+    uint32_t remap_index_4:4;
+    uint32_t remap_index_5:4;
+    uint32_t remap_index_6:4;
+    uint32_t remap_index_7:4;
   }remap_table0;
 
   struct {
-    unsigned int remap_index_8:4;
-    unsigned int remap_index_9:4;
-    unsigned int remap_index_10:4;
-    unsigned int remap_index_11:4;
-    unsigned int remap_index_12:4;
-    unsigned int remap_index_13:4;
-    unsigned int remap_index_14:4;
-    unsigned int remap_index_15:4;
+    uint32_t remap_index_8:4;
+    uint32_t remap_index_9:4;
+    uint32_t remap_index_10:4;
+    uint32_t remap_index_11:4;
+    uint32_t remap_index_12:4;
+    uint32_t remap_index_13:4;
+    uint32_t remap_index_14:4;
+    uint32_t remap_index_15:4;
   } remap_table1;
 
   struct {
-    unsigned int scoreboard_mask:8;
-    unsigned int pad:22;
-    unsigned int type:1;
-    unsigned int enable:1;
+    uint32_t scoreboard_mask:8;
+    uint32_t pad:22;
+    uint32_t type:1;
+    uint32_t enable:1;
   } scoreboard0;
 
   struct {
-    unsigned int ignore;
+    uint32_t ignore;
   } scoreboard1;
 
   struct {
-    unsigned int ignore;
+    uint32_t ignore;
   } scoreboard2;
 
-  unsigned int pad;
+  uint32_t pad;
 };
 
 struct i965_vld_state 
 {
   struct {
-    unsigned int pad6:6;
-    unsigned int scan_order:1;
-    unsigned int intra_vlc_format:1;
-    unsigned int quantizer_scale_type:1;
-    unsigned int concealment_motion_vector:1;
-    unsigned int frame_predict_frame_dct:1;
-    unsigned int top_field_first:1;
-    unsigned int picture_structure:2;
-    unsigned int intra_dc_precision:2;
-    unsigned int f_code_0_0:4;
-    unsigned int f_code_0_1:4;
-    unsigned int f_code_1_0:4;
-    unsigned int f_code_1_1:4;
+    uint32_t pad6:6;
+    uint32_t scan_order:1;
+    uint32_t intra_vlc_format:1;
+    uint32_t quantizer_scale_type:1;
+    uint32_t concealment_motion_vector:1;
+    uint32_t frame_predict_frame_dct:1;
+    uint32_t top_field_first:1;
+    uint32_t picture_structure:2;
+    uint32_t intra_dc_precision:2;
+    uint32_t f_code_0_0:4;
+    uint32_t f_code_0_1:4;
+    uint32_t f_code_1_0:4;
+    uint32_t f_code_1_1:4;
   } vld0;
 
   struct {
-    unsigned int pad2:9;
-    unsigned int picture_coding_type:2;
-    unsigned int pad:21;
+    uint32_t pad2:9;
+    uint32_t picture_coding_type:2;
+    uint32_t pad:21;
   } vld1;
 
   struct {
-    unsigned int index_0:4;
-    unsigned int index_1:4;
-    unsigned int index_2:4;
-    unsigned int index_3:4;
-    unsigned int index_4:4;
-    unsigned int index_5:4;
-    unsigned int index_6:4;
-    unsigned int index_7:4;
+    uint32_t index_0:4;
+    uint32_t index_1:4;
+    uint32_t index_2:4;
+    uint32_t index_3:4;
+    uint32_t index_4:4;
+    uint32_t index_5:4;
+    uint32_t index_6:4;
+    uint32_t index_7:4;
   } desc_remap_table0;
 
   struct {
-    unsigned int index_8:4;
-    unsigned int index_9:4;
-    unsigned int index_10:4;
-    unsigned int index_11:4;
-    unsigned int index_12:4;
-    unsigned int index_13:4;
-    unsigned int index_14:4;
-    unsigned int index_15:4;
+    uint32_t index_8:4;
+    uint32_t index_9:4;
+    uint32_t index_10:4;
+    uint32_t index_11:4;
+    uint32_t index_12:4;
+    uint32_t index_13:4;
+    uint32_t index_14:4;
+    uint32_t index_15:4;
   } desc_remap_table1;
 };
 
 struct i965_interface_descriptor 
 {
   struct {
-    unsigned int grf_reg_blocks:4;
-    unsigned int pad:2;
-    unsigned int kernel_start_pointer:26;
+    uint32_t grf_reg_blocks:4;
+    uint32_t pad:2;
+    uint32_t kernel_start_pointer:26;
   } desc0;
 
   struct {
-    unsigned int pad:7;
-    unsigned int software_exception:1;
-    unsigned int pad2:3;
-    unsigned int maskstack_exception:1;
-    unsigned int pad3:1;
-    unsigned int illegal_opcode_exception:1;
-    unsigned int pad4:2;
-    unsigned int floating_point_mode:1;
-    unsigned int thread_priority:1;
-    unsigned int single_program_flow:1;
-    unsigned int pad5:1;
-    unsigned int const_urb_entry_read_offset:6;
-    unsigned int const_urb_entry_read_len:6;
+    uint32_t pad:7;
+    uint32_t software_exception:1;
+    uint32_t pad2:3;
+    uint32_t maskstack_exception:1;
+    uint32_t pad3:1;
+    uint32_t illegal_opcode_exception:1;
+    uint32_t pad4:2;
+    uint32_t floating_point_mode:1;
+    uint32_t thread_priority:1;
+    uint32_t single_program_flow:1;
+    uint32_t pad5:1;
+    uint32_t const_urb_entry_read_offset:6;
+    uint32_t const_urb_entry_read_len:6;
   } desc1;
 
   struct {
-    unsigned int pad:2;
-    unsigned int sampler_count:3;
-    unsigned int sampler_state_pointer:27;
+    uint32_t pad:2;
+    uint32_t sampler_count:3;
+    uint32_t sampler_state_pointer:27;
   } desc2;
 
   struct {
-    unsigned int binding_table_entry_count:5;
-    unsigned int binding_table_pointer:27;
+    uint32_t binding_table_entry_count:5;
+    uint32_t binding_table_pointer:27;
   } desc3;
 };
 
 struct i965_surface_state 
 {
   struct {
-    unsigned int cube_pos_z:1;
-    unsigned int cube_neg_z:1;
-    unsigned int cube_pos_y:1;
-    unsigned int cube_neg_y:1;
-    unsigned int cube_pos_x:1;
-    unsigned int cube_neg_x:1;
-    unsigned int pad:3;
-    unsigned int render_cache_read_mode:1;
-    unsigned int mipmap_layout_mode:1;
-    unsigned int vert_line_stride_ofs:1;
-    unsigned int vert_line_stride:1;
-    unsigned int color_blend:1;
-    unsigned int writedisable_blue:1;
-    unsigned int writedisable_green:1;
-    unsigned int writedisable_red:1;
-    unsigned int writedisable_alpha:1;
-    unsigned int surface_format:9;
-    unsigned int data_return_format:1;
-    unsigned int pad0:1;
-    unsigned int surface_type:3;
+    uint32_t cube_pos_z:1;
+    uint32_t cube_neg_z:1;
+    uint32_t cube_pos_y:1;
+    uint32_t cube_neg_y:1;
+    uint32_t cube_pos_x:1;
+    uint32_t cube_neg_x:1;
+    uint32_t pad:3;
+    uint32_t render_cache_read_mode:1;
+    uint32_t mipmap_layout_mode:1;
+    uint32_t vert_line_stride_ofs:1;
+    uint32_t vert_line_stride:1;
+    uint32_t color_blend:1;
+    uint32_t writedisable_blue:1;
+    uint32_t writedisable_green:1;
+    uint32_t writedisable_red:1;
+    uint32_t writedisable_alpha:1;
+    uint32_t surface_format:9;
+    uint32_t data_return_format:1;
+    uint32_t pad0:1;
+    uint32_t surface_type:3;
   } ss0;
 
   struct {
-    unsigned int base_addr;
+    uint32_t base_addr;
   } ss1;
 
   struct {
-    unsigned int render_target_rotation:2;
-    unsigned int mip_count:4;
-    unsigned int width:13;
-    unsigned int height:13;
+    uint32_t render_target_rotation:2;
+    uint32_t mip_count:4;
+    uint32_t width:13;
+    uint32_t height:13;
   } ss2;
 
   struct {
-    unsigned int tile_walk:1;
-    unsigned int tiled_surface:1;
-    unsigned int pad:1;
-    unsigned int pitch:18;
-    unsigned int depth:11;
+    uint32_t tile_walk:1;
+    uint32_t tiled_surface:1;
+    uint32_t pad:1;
+    uint32_t pitch:18;
+    uint32_t depth:11;
   } ss3;
 
   struct {
-    unsigned int pad:19;
-    unsigned int min_array_elt:9;
-    unsigned int min_lod:4;
+    uint32_t pad:19;
+    uint32_t min_array_elt:9;
+    uint32_t min_lod:4;
   } ss4;
 
   struct {
-    unsigned int pad:20;
-    unsigned int y_offset:4;
-    unsigned int pad2:1;
-    unsigned int x_offset:7;
+    uint32_t pad:20;
+    uint32_t y_offset:4;
+    uint32_t pad2:1;
+    uint32_t x_offset:7;
   } ss5;
 };
 
 struct thread0
 {
-  unsigned int pad0:1;
-  unsigned int grf_reg_count:3; 
-  unsigned int pad1:2;
-  unsigned int kernel_start_pointer:26; 
+  uint32_t pad0:1;
+  uint32_t grf_reg_count:3; 
+  uint32_t pad1:2;
+  uint32_t kernel_start_pointer:26; 
 };
 
 struct thread1
 {
-  unsigned int ext_halt_exception_enable:1; 
-  unsigned int sw_exception_enable:1; 
-  unsigned int mask_stack_exception_enable:1; 
-  unsigned int timeout_exception_enable:1; 
-  unsigned int illegal_op_exception_enable:1; 
-  unsigned int pad0:3;
-  unsigned int depth_coef_urb_read_offset:6;   /* WM only */
-  unsigned int pad1:2;
-  unsigned int floating_point_mode:1; 
-  unsigned int thread_priority:1; 
-  unsigned int binding_table_entry_count:8; 
-  unsigned int pad3:5;
-  unsigned int single_program_flow:1; 
+  uint32_t ext_halt_exception_enable:1; 
+  uint32_t sw_exception_enable:1; 
+  uint32_t mask_stack_exception_enable:1; 
+  uint32_t timeout_exception_enable:1; 
+  uint32_t illegal_op_exception_enable:1; 
+  uint32_t pad0:3;
+  uint32_t depth_coef_urb_read_offset:6;       /* WM only */
+  uint32_t pad1:2;
+  uint32_t floating_point_mode:1; 
+  uint32_t thread_priority:1; 
+  uint32_t binding_table_entry_count:8; 
+  uint32_t pad3:5;
+  uint32_t single_program_flow:1; 
 };
 
 struct thread2
 {
-  unsigned int per_thread_scratch_space:4; 
-  unsigned int pad0:6;
-  unsigned int scratch_space_base_pointer:22; 
+  uint32_t per_thread_scratch_space:4; 
+  uint32_t pad0:6;
+  uint32_t scratch_space_base_pointer:22; 
 };
 
 struct thread3
 {
-  unsigned int dispatch_grf_start_reg:4; 
-  unsigned int urb_entry_read_offset:6; 
-  unsigned int pad0:1;
-  unsigned int urb_entry_read_length:6; 
-  unsigned int pad1:1;
-  unsigned int const_urb_entry_read_offset:6; 
-  unsigned int pad2:1;
-  unsigned int const_urb_entry_read_length:6; 
-  unsigned int pad3:1;
+  uint32_t dispatch_grf_start_reg:4; 
+  uint32_t urb_entry_read_offset:6; 
+  uint32_t pad0:1;
+  uint32_t urb_entry_read_length:6; 
+  uint32_t pad1:1;
+  uint32_t const_urb_entry_read_offset:6; 
+  uint32_t pad2:1;
+  uint32_t const_urb_entry_read_length:6; 
+  uint32_t pad3:1;
 };
 
 struct i965_vs_unit_state
@@ -298,26 +300,26 @@ struct i965_vs_unit_state
   struct thread3 thread3;
 
   struct {
-    unsigned int pad0:10;
-    unsigned int stats_enable:1; 
-    unsigned int nr_urb_entries:7; 
-    unsigned int pad1:1;
-    unsigned int urb_entry_allocation_size:5; 
-    unsigned int pad2:1;
-    unsigned int max_threads:4; 
-    unsigned int pad3:3;
+    uint32_t pad0:10;
+    uint32_t stats_enable:1; 
+    uint32_t nr_urb_entries:7; 
+    uint32_t pad1:1;
+    uint32_t urb_entry_allocation_size:5; 
+    uint32_t pad2:1;
+    uint32_t max_threads:4; 
+    uint32_t pad3:3;
   } thread4;   
 
   struct {
-    unsigned int sampler_count:3; 
-    unsigned int pad0:2;
-    unsigned int sampler_state_pointer:27; 
+    uint32_t sampler_count:3; 
+    uint32_t pad0:2;
+    uint32_t sampler_state_pointer:27; 
   } vs5;
 
   struct {
-    unsigned int vs_enable:1; 
-    unsigned int vert_cache_disable:1; 
-    unsigned int pad0:30;
+    uint32_t vs_enable:1; 
+    uint32_t vert_cache_disable:1; 
+    uint32_t pad0:30;
   } vs6;
 };
 
@@ -329,28 +331,28 @@ struct i965_gs_unit_state
   struct thread3 thread3;
 
   struct {
-    unsigned int pad0:10;
-    unsigned int stats_enable:1; 
-    unsigned int nr_urb_entries:7; 
-    unsigned int pad1:1;
-    unsigned int urb_entry_allocation_size:5; 
-    unsigned int pad2:1;
-    unsigned int max_threads:1; 
-    unsigned int pad3:6;
+    uint32_t pad0:10;
+    uint32_t stats_enable:1; 
+    uint32_t nr_urb_entries:7; 
+    uint32_t pad1:1;
+    uint32_t urb_entry_allocation_size:5; 
+    uint32_t pad2:1;
+    uint32_t max_threads:1; 
+    uint32_t pad3:6;
   } thread4;   
 
   struct {
-    unsigned int sampler_count:3; 
-    unsigned int pad0:2;
-    unsigned int sampler_state_pointer:27; 
+    uint32_t sampler_count:3; 
+    uint32_t pad0:2;
+    uint32_t sampler_state_pointer:27; 
   } gs5;
 
 
   struct {
-    unsigned int max_vp_index:4; 
-    unsigned int pad0:26;
-    unsigned int reorder_enable:1; 
-    unsigned int pad1:1;
+    uint32_t max_vp_index:4; 
+    uint32_t pad0:26;
+    uint32_t reorder_enable:1; 
+    uint32_t pad1:1;
   } gs6;
 };
 
@@ -362,34 +364,34 @@ struct i965_clip_unit_state
   struct thread3 thread3;
 
   struct {
-    unsigned int pad0:9;
-    unsigned int gs_output_stats:1; /* not always */
-    unsigned int stats_enable:1; 
-    unsigned int nr_urb_entries:7; 
-    unsigned int pad1:1;
-    unsigned int urb_entry_allocation_size:5; 
-    unsigned int pad2:1;
-    unsigned int max_threads:6;        /* may be less */
-    unsigned int pad3:1;
+    uint32_t pad0:9;
+    uint32_t gs_output_stats:1; /* not always */
+    uint32_t stats_enable:1; 
+    uint32_t nr_urb_entries:7; 
+    uint32_t pad1:1;
+    uint32_t urb_entry_allocation_size:5; 
+    uint32_t pad2:1;
+    uint32_t max_threads:6;    /* may be less */
+    uint32_t pad3:1;
   } thread4;   
 
   struct {
-    unsigned int pad0:13;
-    unsigned int clip_mode:3; 
-    unsigned int userclip_enable_flags:8; 
-    unsigned int userclip_must_clip:1; 
-    unsigned int pad1:1;
-    unsigned int guard_band_enable:1; 
-    unsigned int viewport_z_clip_enable:1; 
-    unsigned int viewport_xy_clip_enable:1; 
-    unsigned int vertex_position_space:1; 
-    unsigned int api_mode:1; 
-    unsigned int pad2:1;
+    uint32_t pad0:13;
+    uint32_t clip_mode:3; 
+    uint32_t userclip_enable_flags:8; 
+    uint32_t userclip_must_clip:1; 
+    uint32_t pad1:1;
+    uint32_t guard_band_enable:1; 
+    uint32_t viewport_z_clip_enable:1; 
+    uint32_t viewport_xy_clip_enable:1; 
+    uint32_t vertex_position_space:1; 
+    uint32_t api_mode:1; 
+    uint32_t pad2:1;
   } clip5;
 
   struct {
-    unsigned int pad0:5;
-    unsigned int clipper_viewport_state_ptr:27; 
+    uint32_t pad0:5;
+    uint32_t clipper_viewport_state_ptr:27; 
   } clip6;
 
 
@@ -403,109 +405,109 @@ struct i965_sf_unit_state
 {
   struct thread0 thread0;
   struct {
-    unsigned int pad0:7;
-    unsigned int sw_exception_enable:1; 
-    unsigned int pad1:3;
-    unsigned int mask_stack_exception_enable:1; 
-    unsigned int pad2:1;
-    unsigned int illegal_op_exception_enable:1; 
-    unsigned int pad3:2;
-    unsigned int floating_point_mode:1; 
-    unsigned int thread_priority:1; 
-    unsigned int binding_table_entry_count:8; 
-    unsigned int pad4:5;
-    unsigned int single_program_flow:1; 
+    uint32_t pad0:7;
+    uint32_t sw_exception_enable:1; 
+    uint32_t pad1:3;
+    uint32_t mask_stack_exception_enable:1; 
+    uint32_t pad2:1;
+    uint32_t illegal_op_exception_enable:1; 
+    uint32_t pad3:2;
+    uint32_t floating_point_mode:1; 
+    uint32_t thread_priority:1; 
+    uint32_t binding_table_entry_count:8; 
+    uint32_t pad4:5;
+    uint32_t single_program_flow:1; 
   } sf1;
 
   struct thread2 thread2;
   struct thread3 thread3;
 
   struct {
-    unsigned int pad0:10;
-    unsigned int stats_enable:1; 
-    unsigned int nr_urb_entries:7; 
-    unsigned int pad1:1;
-    unsigned int urb_entry_allocation_size:5; 
-    unsigned int pad2:1;
-    unsigned int max_threads:6; 
-    unsigned int pad3:1;
+    uint32_t pad0:10;
+    uint32_t stats_enable:1; 
+    uint32_t nr_urb_entries:7; 
+    uint32_t pad1:1;
+    uint32_t urb_entry_allocation_size:5; 
+    uint32_t pad2:1;
+    uint32_t max_threads:6; 
+    uint32_t pad3:1;
   } thread4;   
 
   struct {
-    unsigned int front_winding:1; 
-    unsigned int viewport_transform:1; 
-    unsigned int pad0:3;
-    unsigned int sf_viewport_state_offset:27; 
+    uint32_t front_winding:1; 
+    uint32_t viewport_transform:1; 
+    uint32_t pad0:3;
+    uint32_t sf_viewport_state_offset:27; 
   } sf5;
 
   struct {
-    unsigned int pad0:9;
-    unsigned int dest_org_vbias:4; 
-    unsigned int dest_org_hbias:4; 
-    unsigned int scissor:1; 
-    unsigned int disable_2x2_trifilter:1; 
-    unsigned int disable_zero_pix_trifilter:1; 
-    unsigned int point_rast_rule:2; 
-    unsigned int line_endcap_aa_region_width:2; 
-    unsigned int line_width:4; 
-    unsigned int fast_scissor_disable:1; 
-    unsigned int cull_mode:2; 
-    unsigned int aa_enable:1; 
+    uint32_t pad0:9;
+    uint32_t dest_org_vbias:4; 
+    uint32_t dest_org_hbias:4; 
+    uint32_t scissor:1; 
+    uint32_t disable_2x2_trifilter:1; 
+    uint32_t disable_zero_pix_trifilter:1; 
+    uint32_t point_rast_rule:2; 
+    uint32_t line_endcap_aa_region_width:2; 
+    uint32_t line_width:4; 
+    uint32_t fast_scissor_disable:1; 
+    uint32_t cull_mode:2; 
+    uint32_t aa_enable:1; 
   } sf6;
 
   struct {
-    unsigned int point_size:11; 
-    unsigned int use_point_size_state:1; 
-    unsigned int subpixel_precision:1; 
-    unsigned int sprite_point:1; 
-    unsigned int pad0:11;
-    unsigned int trifan_pv:2; 
-    unsigned int linestrip_pv:2; 
-    unsigned int tristrip_pv:2; 
-    unsigned int line_last_pixel_enable:1; 
+    uint32_t point_size:11; 
+    uint32_t use_point_size_state:1; 
+    uint32_t subpixel_precision:1; 
+    uint32_t sprite_point:1; 
+    uint32_t pad0:11;
+    uint32_t trifan_pv:2; 
+    uint32_t linestrip_pv:2; 
+    uint32_t tristrip_pv:2; 
+    uint32_t line_last_pixel_enable:1; 
   } sf7;
 };
 
 struct i965_sampler_state
 {
   struct {
-    unsigned int shadow_function:3; 
-    unsigned int lod_bias:11; 
-    unsigned int min_filter:3; 
-    unsigned int mag_filter:3; 
-    unsigned int mip_filter:2; 
-    unsigned int base_level:5; 
-    unsigned int pad:1;
-    unsigned int lod_preclamp:1; 
-    unsigned int border_color_mode:1; 
-    unsigned int pad0:1;
-    unsigned int disable:1; 
+    uint32_t shadow_function:3; 
+    uint32_t lod_bias:11; 
+    uint32_t min_filter:3; 
+    uint32_t mag_filter:3; 
+    uint32_t mip_filter:2; 
+    uint32_t base_level:5; 
+    uint32_t pad:1;
+    uint32_t lod_preclamp:1; 
+    uint32_t border_color_mode:1; 
+    uint32_t pad0:1;
+    uint32_t disable:1; 
   } ss0;
 
   struct {
-    unsigned int r_wrap_mode:3; 
-    unsigned int t_wrap_mode:3; 
-    unsigned int s_wrap_mode:3; 
-    unsigned int pad:3;
-    unsigned int max_lod:10; 
-    unsigned int min_lod:10; 
+    uint32_t r_wrap_mode:3; 
+    uint32_t t_wrap_mode:3; 
+    uint32_t s_wrap_mode:3; 
+    uint32_t pad:3;
+    uint32_t max_lod:10; 
+    uint32_t min_lod:10; 
   } ss1;
 
 
   struct {
-    unsigned int pad:5;
-    unsigned int border_color_pointer:27; 
+    uint32_t pad:5;
+    uint32_t border_color_pointer:27; 
   } ss2;
 
   struct {
-    unsigned int gen6_non_normalized:1;
-    unsigned int pad:18;
-    unsigned int max_aniso:3; 
-    unsigned int chroma_key_mode:1; 
-    unsigned int chroma_key_index:2; 
-    unsigned int chroma_key_enable:1; 
-    unsigned int monochrome_filter_width:3; 
-    unsigned int monochrome_filter_height:3; 
+    uint32_t gen6_non_normalized:1;
+    uint32_t pad:18;
+    uint32_t max_aniso:3; 
+    uint32_t chroma_key_mode:1; 
+    uint32_t chroma_key_index:2; 
+    uint32_t chroma_key_enable:1; 
+    uint32_t monochrome_filter_width:3; 
+    uint32_t monochrome_filter_height:3; 
   } ss3;
 };
 
@@ -517,31 +519,31 @@ struct i965_wm_unit_state
   struct thread3 thread3;
 
   struct {
-    unsigned int stats_enable:1; 
-    unsigned int pad0:1;
-    unsigned int sampler_count:3; 
-    unsigned int sampler_state_pointer:27; 
+    uint32_t stats_enable:1; 
+    uint32_t pad0:1;
+    uint32_t sampler_count:3; 
+    uint32_t sampler_state_pointer:27; 
   } wm4;
 
   struct {
-    unsigned int enable_8_pix:1; 
-    unsigned int enable_16_pix:1; 
-    unsigned int enable_32_pix:1; 
-    unsigned int pad0:7;
-    unsigned int legacy_global_depth_bias:1; 
-    unsigned int line_stipple:1; 
-    unsigned int depth_offset:1; 
-    unsigned int polygon_stipple:1; 
-    unsigned int line_aa_region_width:2; 
-    unsigned int line_endcap_aa_region_width:2; 
-    unsigned int early_depth_test:1; 
-    unsigned int thread_dispatch_enable:1; 
-    unsigned int program_uses_depth:1; 
-    unsigned int program_computes_depth:1; 
-    unsigned int program_uses_killpixel:1; 
-    unsigned int legacy_line_rast: 1; 
-    unsigned int transposed_urb_read:1; 
-    unsigned int max_threads:7; 
+    uint32_t enable_8_pix:1; 
+    uint32_t enable_16_pix:1; 
+    uint32_t enable_32_pix:1; 
+    uint32_t pad0:7;
+    uint32_t legacy_global_depth_bias:1; 
+    uint32_t line_stipple:1; 
+    uint32_t depth_offset:1; 
+    uint32_t polygon_stipple:1; 
+    uint32_t line_aa_region_width:2; 
+    uint32_t line_endcap_aa_region_width:2; 
+    uint32_t early_depth_test:1; 
+    uint32_t thread_dispatch_enable:1; 
+    uint32_t program_uses_depth:1; 
+    uint32_t program_computes_depth:1; 
+    uint32_t program_uses_killpixel:1; 
+    uint32_t legacy_line_rast: 1; 
+    uint32_t transposed_urb_read:1; 
+    uint32_t max_threads:7; 
   } wm5;
 
   float global_depth_offset_constant;  
@@ -557,78 +559,78 @@ struct i965_cc_viewport
 struct i965_cc_unit_state
 {
   struct {
-    unsigned int pad0:3;
-    unsigned int bf_stencil_pass_depth_pass_op:3; 
-    unsigned int bf_stencil_pass_depth_fail_op:3; 
-    unsigned int bf_stencil_fail_op:3; 
-    unsigned int bf_stencil_func:3; 
-    unsigned int bf_stencil_enable:1; 
-    unsigned int pad1:2;
-    unsigned int stencil_write_enable:1; 
-    unsigned int stencil_pass_depth_pass_op:3; 
-    unsigned int stencil_pass_depth_fail_op:3; 
-    unsigned int stencil_fail_op:3; 
-    unsigned int stencil_func:3; 
-    unsigned int stencil_enable:1; 
+    uint32_t pad0:3;
+    uint32_t bf_stencil_pass_depth_pass_op:3; 
+    uint32_t bf_stencil_pass_depth_fail_op:3; 
+    uint32_t bf_stencil_fail_op:3; 
+    uint32_t bf_stencil_func:3; 
+    uint32_t bf_stencil_enable:1; 
+    uint32_t pad1:2;
+    uint32_t stencil_write_enable:1; 
+    uint32_t stencil_pass_depth_pass_op:3; 
+    uint32_t stencil_pass_depth_fail_op:3; 
+    uint32_t stencil_fail_op:3; 
+    uint32_t stencil_func:3; 
+    uint32_t stencil_enable:1; 
   } cc0;
 
 
   struct {
-    unsigned int bf_stencil_ref:8; 
-    unsigned int stencil_write_mask:8; 
-    unsigned int stencil_test_mask:8; 
-    unsigned int stencil_ref:8; 
+    uint32_t bf_stencil_ref:8; 
+    uint32_t stencil_write_mask:8; 
+    uint32_t stencil_test_mask:8; 
+    uint32_t stencil_ref:8; 
   } cc1;
 
 
   struct {
-    unsigned int logicop_enable:1; 
-    unsigned int pad0:10;
-    unsigned int depth_write_enable:1; 
-    unsigned int depth_test_function:3; 
-    unsigned int depth_test:1; 
-    unsigned int bf_stencil_write_mask:8; 
-    unsigned int bf_stencil_test_mask:8; 
+    uint32_t logicop_enable:1; 
+    uint32_t pad0:10;
+    uint32_t depth_write_enable:1; 
+    uint32_t depth_test_function:3; 
+    uint32_t depth_test:1; 
+    uint32_t bf_stencil_write_mask:8; 
+    uint32_t bf_stencil_test_mask:8; 
   } cc2;
 
 
   struct {
-    unsigned int pad0:8;
-    unsigned int alpha_test_func:3; 
-    unsigned int alpha_test:1; 
-    unsigned int blend_enable:1; 
-    unsigned int ia_blend_enable:1; 
-    unsigned int pad1:1;
-    unsigned int alpha_test_format:1;
-    unsigned int pad2:16;
+    uint32_t pad0:8;
+    uint32_t alpha_test_func:3; 
+    uint32_t alpha_test:1; 
+    uint32_t blend_enable:1; 
+    uint32_t ia_blend_enable:1; 
+    uint32_t pad1:1;
+    uint32_t alpha_test_format:1;
+    uint32_t pad2:16;
   } cc3;
 
   struct {
-    unsigned int pad0:5; 
-    unsigned int cc_viewport_state_offset:27; 
+    uint32_t pad0:5; 
+    uint32_t cc_viewport_state_offset:27; 
   } cc4;
 
   struct {
-    unsigned int pad0:2;
-    unsigned int ia_dest_blend_factor:5; 
-    unsigned int ia_src_blend_factor:5; 
-    unsigned int ia_blend_function:3; 
-    unsigned int statistics_enable:1; 
-    unsigned int logicop_func:4; 
-    unsigned int pad1:11;
-    unsigned int dither_enable:1; 
+    uint32_t pad0:2;
+    uint32_t ia_dest_blend_factor:5; 
+    uint32_t ia_src_blend_factor:5; 
+    uint32_t ia_blend_function:3; 
+    uint32_t statistics_enable:1; 
+    uint32_t logicop_func:4; 
+    uint32_t pad1:11;
+    uint32_t dither_enable:1; 
   } cc5;
 
   struct {
-    unsigned int clamp_post_alpha_blend:1; 
-    unsigned int clamp_pre_alpha_blend:1; 
-    unsigned int clamp_range:2; 
-    unsigned int pad0:11;
-    unsigned int y_dither_offset:2; 
-    unsigned int x_dither_offset:2; 
-    unsigned int dest_blend_factor:5; 
-    unsigned int src_blend_factor:5; 
-    unsigned int blend_function:3; 
+    uint32_t clamp_post_alpha_blend:1; 
+    uint32_t clamp_pre_alpha_blend:1; 
+    uint32_t clamp_range:2; 
+    uint32_t pad0:11;
+    uint32_t y_dither_offset:2; 
+    uint32_t x_dither_offset:2; 
+    uint32_t dest_blend_factor:5; 
+    uint32_t src_blend_factor:5; 
+    uint32_t blend_function:3; 
   } cc6;
 
   struct {
@@ -639,4 +641,62 @@ struct i965_cc_unit_state
   } cc7;
 };
 
+#define BITFIELD_BIT(X) 1
+#define BITFIELD_RANGE(X,Y) ((Y) - (X) + 1)
+
+typedef struct i965_pipe_control
+{
+  struct
+  {
+    uint32_t length                              : BITFIELD_RANGE(0, 7);
+    uint32_t reserved                            : BITFIELD_RANGE(8, 15);
+    uint32_t instruction_subopcode               : BITFIELD_RANGE(16, 23);
+    uint32_t instruction_opcode                  : BITFIELD_RANGE(24, 26);
+    uint32_t instruction_pipeline                : BITFIELD_RANGE(27, 28);
+    uint32_t instruction_type                    : BITFIELD_RANGE(29, 31);
+  } dw0;
+
+  struct
+  {
+    uint32_t depth_cache_flush_enable            : BITFIELD_BIT(0);
+    uint32_t stall_at_pixel_scoreboard           : BITFIELD_BIT(1);
+    uint32_t state_cache_invalidation_enable     : BITFIELD_BIT(2);
+    uint32_t constant_cache_invalidation_enable  : BITFIELD_BIT(3);
+    uint32_t vf_cache_invalidation_enable        : BITFIELD_BIT(4);
+    uint32_t dc_flush_enable                     : BITFIELD_BIT(5);
+    uint32_t protected_memory_app_id             : BITFIELD_BIT(6);
+    uint32_t pipe_control_flush_enable           : BITFIELD_BIT(7);
+    uint32_t notify_enable                       : BITFIELD_BIT(8);
+    uint32_t indirect_state_pointers_disable     : BITFIELD_BIT(9);
+    uint32_t texture_cache_invalidation_enable   : BITFIELD_BIT(10);
+    uint32_t instruction_cache_invalidate_enable : BITFIELD_BIT(11);
+    uint32_t render_target_cache_flush_enable    : BITFIELD_BIT(12);
+    uint32_t depth_stall_enable                  : BITFIELD_BIT(13);
+    uint32_t post_sync_operation                 : BITFIELD_RANGE(14, 15);
+    uint32_t generic_media_state_clear           : BITFIELD_BIT(16);
+    uint32_t synchronize_gfdt_surface            : BITFIELD_BIT(17);
+    uint32_t tlb_invalidate                      : BITFIELD_BIT(18);
+    uint32_t global_snapshot_count_reset         : BITFIELD_BIT(19);
+    uint32_t cs_stall                            : BITFIELD_BIT(20);
+    uint32_t store_data_index                    : BITFIELD_BIT(21);
+    uint32_t protected_memory_enable             : BITFIELD_BIT(22);
+    uint32_t reserved                            : BITFIELD_RANGE(23, 31);
+  } dw1;
+
+  struct
+  {
+    uint32_t reserved                            : BITFIELD_RANGE(0, 1);
+    uint32_t destination_address_type            : BITFIELD_BIT(2);
+    uint32_t address                             : BITFIELD_RANGE(3, 31);
+  } dw2;
+
+  struct
+  {
+    uint64_t data;
+  } qw0;
+} i965_pipe_control_t;
+
+#undef BITFIELD_BIT
+#undef BITFIELD_RANGE
+
 #endif /* __GENX_STRUCTS_H__ */