arm64: dts: renesas: rzg2l-smarc: Enable RSPI1 on carrier board
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Wed, 17 Nov 2021 01:12:47 +0000 (01:12 +0000)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Fri, 19 Nov 2021 09:52:21 +0000 (10:52 +0100)
RSPI1 (SPI1) interface is available on PMOD0 connector (J1) on the
carrier board.  This patch adds pinmux and spi1 nodes to the carrier
board dtsi file.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20211117011247.27621-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi

index 4c32f06..6f2a8bd 100644 (file)
                input-enable;
        };
 
+       spi1_pins: spi1 {
+               pinmux = <RZG2L_PORT_PINMUX(44, 0, 1)>, /* CK */
+                        <RZG2L_PORT_PINMUX(44, 1, 1)>, /* MOSI */
+                        <RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */
+                        <RZG2L_PORT_PINMUX(44, 3, 1)>; /* SSL */
+       };
+
        ssi0_pins: ssi0 {
                pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */
                         <RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */
        status = "okay";
 };
 
+&spi1 {
+       pinctrl-0 = <&spi1_pins>;
+       pinctrl-names = "default";
+
+       status = "okay";
+};
+
 &ssi0 {
        pinctrl-0 = <&ssi0_pins>;
        pinctrl-names = "default";