net/mlx5: Add misc4 to mlx5_ifc_fte_match_param_bits
authorMuhammad Sammar <muhammads@nvidia.com>
Fri, 20 Nov 2020 23:03:27 +0000 (15:03 -0800)
committerSaeed Mahameed <saeedm@nvidia.com>
Fri, 27 Nov 2020 02:43:47 +0000 (18:43 -0800)
Add misc4 match params to enable matching on prog_sample_fields.

Signed-off-by: Muhammad Sammar <muhammads@nvidia.com>
Reviewed-by: Alex Vesker <valex@nvidia.com>
Reviewed-by: Mark Bloch <mbloch@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
drivers/net/ethernet/mellanox/mlx5/core/fs_core.h
include/linux/mlx5/device.h
include/linux/mlx5/mlx5_ifc.h
include/uapi/rdma/mlx5_user_ioctl_cmds.h

index afe7f0b..b24a984 100644 (file)
@@ -194,7 +194,7 @@ struct mlx5_ft_underlay_qp {
        u32 qpn;
 };
 
-#define MLX5_FTE_MATCH_PARAM_RESERVED  reserved_at_a00
+#define MLX5_FTE_MATCH_PARAM_RESERVED  reserved_at_c00
 /* Calculate the fte_match_param length and without the reserved length.
  * Make sure the reserved field is the last.
  */
index cf82436..e9639c4 100644 (file)
@@ -1076,6 +1076,7 @@ enum {
        MLX5_MATCH_INNER_HEADERS        = 1 << 2,
        MLX5_MATCH_MISC_PARAMETERS_2    = 1 << 3,
        MLX5_MATCH_MISC_PARAMETERS_3    = 1 << 4,
+       MLX5_MATCH_MISC_PARAMETERS_4    = 1 << 5,
 };
 
 enum {
index 2f2add4..11c24fa 100644 (file)
@@ -623,6 +623,26 @@ struct mlx5_ifc_fte_match_set_misc3_bits {
        u8         reserved_at_140[0xc0];
 };
 
+struct mlx5_ifc_fte_match_set_misc4_bits {
+       u8         prog_sample_field_value_0[0x20];
+
+       u8         prog_sample_field_id_0[0x20];
+
+       u8         prog_sample_field_value_1[0x20];
+
+       u8         prog_sample_field_id_1[0x20];
+
+       u8         prog_sample_field_value_2[0x20];
+
+       u8         prog_sample_field_id_2[0x20];
+
+       u8         prog_sample_field_value_3[0x20];
+
+       u8         prog_sample_field_id_3[0x20];
+
+       u8         reserved_at_100[0x100];
+};
+
 struct mlx5_ifc_cmd_pas_bits {
        u8         pa_h[0x20];
 
@@ -1669,7 +1689,9 @@ struct mlx5_ifc_fte_match_param_bits {
 
        struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
 
-       u8         reserved_at_a00[0x600];
+       struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
+
+       u8         reserved_at_c00[0x400];
 };
 
 enum {
@@ -5462,6 +5484,7 @@ enum {
        MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
        MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
        MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
+       MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
 };
 
 struct mlx5_ifc_query_flow_group_out_bits {
index e24d66d..3fd9b38 100644 (file)
@@ -232,7 +232,7 @@ enum mlx5_ib_device_query_context_attrs {
        MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX = (1U << UVERBS_ID_NS_SHIFT),
 };
 
-#define MLX5_IB_DW_MATCH_PARAM 0x80
+#define MLX5_IB_DW_MATCH_PARAM 0x90
 
 struct mlx5_ib_match_params {
        __u32   match_params[MLX5_IB_DW_MATCH_PARAM];