As for other clock domains.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
uint32_t format_revision;
uint32_t content_revision;
uint32_t fclk;
+ uint32_t lclk;
};
enum smu_table_id
(uint8_t)SMU11_SYSPLL1_2_ID,
&smu->smu_table.boot_values.fclk);
+ smu_v11_0_atom_get_smu_clockinfo(smu->adev,
+ (uint8_t)SMU11_SYSPLL3_1_LCLK_ID,
+ (uint8_t)SMU11_SYSPLL3_1_ID,
+ &smu->smu_table.boot_values.lclk);
+
return 0;
}