InferAddressSpaces: Fix assert with unreachable code

Invalid IR in unreachable code is technically valid IR. In this case,
the address space of the value was never inferred, and we tried to
rewrite it with an invalid address space value which would assert.

diff --git a/llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp b/llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp
index db9cc58..0ed6b59 100644 (file)
--- a/llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp
+++ b/llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp
@@ -997,6 +997,12 @@ bool InferAddressSpaces::rewriteWithNewAddressSpaces(
   SmallVector<const Use *, 32> UndefUsesToFix;
   for (Value* V : Postorder) {
     unsigned NewAddrSpace = InferredAddrSpace.lookup(V);
+
+    // In some degenerate cases (e.g. invalid IR in unreachable code), we may
+    // not even infer the value to have its original address space.
+    if (NewAddrSpace == UninitializedAddressSpace)
+      continue;
+
     if (V->getType()->getPointerAddressSpace() != NewAddrSpace) {
       Value *New = cloneValueWithNewAddressSpace(
           V, NewAddrSpace, ValueWithNewAddrSpace, &UndefUsesToFix);

diff --git a/llvm/test/Transforms/InferAddressSpaces/AMDGPU/self-phi.ll b/llvm/test/Transforms/InferAddressSpaces/AMDGPU/self-phi.ll
new file mode 100644 (file)
index 0000000..2f6496a
--- /dev/null
+++ b/llvm/test/Transforms/InferAddressSpaces/AMDGPU/self-phi.ll
@@ -0,0 +1,28 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -S -infer-address-spaces %s | FileCheck %s
+
+define amdgpu_kernel void @phi_self(i8 addrspace(1)* %arg) {
+; CHECK-LABEL: @phi_self(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br label [[LOOP:%.*]]
+; CHECK:       loop:
+; CHECK-NEXT:    [[I:%.*]] = phi i8 addrspace(1)* [ [[I]], [[LOOP]] ], [ [[ARG:%.*]], [[ENTRY:%.*]] ]
+; CHECK-NEXT:    [[I1:%.*]] = load i8, i8 addrspace(1)* [[I]], align 1
+; CHECK-NEXT:    [[I2:%.*]] = icmp eq i8 [[I1]], 0
+; CHECK-NEXT:    br i1 [[I2]], label [[LOOP]], label [[RET:%.*]]
+; CHECK:       ret:
+; CHECK-NEXT:    ret void
+;
+entry:
+  %cast = addrspacecast i8 addrspace(1)* %arg to i8*
+  br label %loop
+
+loop:
+  %i = phi i8* [%i, %loop], [%cast, %entry]
+  %i1 = load i8, i8* %i, align 1
+  %i2 = icmp eq i8 %i1, 0
+  br i1 %i2, label %loop, label %ret
+
+ret:
+  ret void
+}

diff --git a/llvm/test/Transforms/InferAddressSpaces/AMDGPU/unreachable-code-assert.ll b/llvm/test/Transforms/InferAddressSpaces/AMDGPU/unreachable-code-assert.ll
new file mode 100644 (file)
index 0000000..73001b5
--- /dev/null
+++ b/llvm/test/Transforms/InferAddressSpaces/AMDGPU/unreachable-code-assert.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -S -infer-address-spaces %s | FileCheck %s
+
+define amdgpu_kernel void @subclass_data_assert() {
+; CHECK-LABEL: @subclass_data_assert(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    unreachable
+; CHECK:       strlen.while11:
+; CHECK-NEXT:    [[I:%.*]] = getelementptr i8, i8* [[I]], i64 1
+; CHECK-NEXT:    [[I1:%.*]] = load i8, i8* [[I]], align 1
+; CHECK-NEXT:    [[I2:%.*]] = icmp eq i8 [[I1]], 0
+; CHECK-NEXT:    br i1 [[I2]], label [[STRLEN_WHILE_DONE12:%.*]], label [[STRLEN_WHILE11:%.*]]
+; CHECK:       strlen.while.done12:
+; CHECK-NEXT:    ret void
+;
+entry:
+  unreachable
+
+strlen.while11:                                   ; preds = %strlen.while11
+  %i = getelementptr i8, i8* %i, i64 1
+  %i1 = load i8, i8* %i, align 1
+  %i2 = icmp eq i8 %i1, 0
+  br i1 %i2, label %strlen.while.done12, label %strlen.while11
+
+strlen.while.done12:                              ; preds = %strlen.while11
+  ret void
+}