drm/vc4: Increase the core clock based on HVS load
authorMaxime Ripard <maxime@cerno.tech>
Wed, 26 May 2021 14:13:02 +0000 (16:13 +0200)
committerDom Cobley <popcornmix@gmail.com>
Mon, 21 Mar 2022 16:04:18 +0000 (16:04 +0000)
Depending on a given HVS output (HVS to PixelValves) and input (planes
attached to a channel) load, the HVS needs for the core clock to be
raised above its boot time default.

Failing to do so will result in a vblank timeout and a stalled display
pipeline.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>
drivers/gpu/drm/vc4/vc4_drv.h
drivers/gpu/drm/vc4/vc4_kms.c

index 4329e09..3921959 100644 (file)
@@ -321,6 +321,7 @@ struct vc4_hvs {
        u32 __iomem *dlist;
 
        struct clk *core_clk;
+       struct clk_request *core_req;
 
        /* Memory manager for CRTCs to allocate space in the display
         * list.  Units are dwords.
index 87e51d4..3453932 100644 (file)
@@ -391,6 +391,11 @@ static void vc4_atomic_commit_tail(struct drm_atomic_state *state)
                                                new_hvs_state->core_clock_rate);
 
                core_req = clk_request_start(hvs->core_clk, core_rate);
+               /*
+                * And remove the previous one based on the HVS
+                * requirements if any.
+                */
+               clk_request_done(hvs->core_req);
        }
 
        drm_atomic_helper_commit_modeset_disables(dev, state);
@@ -418,6 +423,14 @@ static void vc4_atomic_commit_tail(struct drm_atomic_state *state)
                drm_dbg(dev, "Running the core clock at %lu Hz\n",
                        new_hvs_state->core_clock_rate);
 
+               /*
+                * Request a clock rate based on the current HVS
+                * requirements.
+                */
+               hvs->core_req = clk_request_start(hvs->core_clk,
+                                                 new_hvs_state->core_clock_rate);
+
+               /* And drop the temporary request */
                clk_request_done(core_req);
        }
 }