powerpc/feature: Remove CPU_FTR_NODSISRALIGN
authorChristophe Leroy <christophe.leroy@csgroup.eu>
Tue, 13 Oct 2020 11:11:21 +0000 (11:11 +0000)
committerMichael Ellerman <mpe@ellerman.id.au>
Thu, 3 Dec 2020 14:01:34 +0000 (01:01 +1100)
CPU_FTR_NODSISRALIGN has not been used since
commit 31bfdb036f12 ("powerpc: Use instruction emulation
infrastructure to handle alignment faults")

Remove it.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/05d98136b24bbf11525445414bb18cffe2724f48.1602587470.git.christophe.leroy@csgroup.eu
arch/powerpc/include/asm/cputable.h
arch/powerpc/kernel/dt_cpu_ftrs.c
arch/powerpc/kernel/prom.c

index 47e87e5..7becef1 100644 (file)
@@ -137,7 +137,7 @@ static inline void cpu_feature_keys_init(void) { }
 #define CPU_FTR_DBELL                  ASM_CONST(0x00000004)
 #define CPU_FTR_CAN_NAP                        ASM_CONST(0x00000008)
 #define CPU_FTR_DEBUG_LVL_EXC          ASM_CONST(0x00000010)
-#define CPU_FTR_NODSISRALIGN           ASM_CONST(0x00000020)
+// ASM_CONST(0x00000020) Free
 #define CPU_FTR_FPU_UNAVAILABLE                ASM_CONST(0x00000040)
 #define CPU_FTR_LWSYNC                 ASM_CONST(0x00000080)
 #define CPU_FTR_NOEXECUTE              ASM_CONST(0x00000100)
@@ -219,7 +219,7 @@ static inline void cpu_feature_keys_init(void) { }
 
 #ifndef __ASSEMBLY__
 
-#define CPU_FTR_PPCAS_ARCH_V2  (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
+#define CPU_FTR_PPCAS_ARCH_V2  (CPU_FTR_NOEXECUTE)
 
 /* We only set the altivec features if the kernel was compiled with altivec
  * support
@@ -376,33 +376,33 @@ static inline void cpu_feature_keys_init(void) { }
            CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE  | CPU_FTR_NOEXECUTE)
 #define CPU_FTRS_CLASSIC32     (CPU_FTR_COMMON)
 #define CPU_FTRS_8XX   (CPU_FTR_NOEXECUTE)
-#define CPU_FTRS_40X   (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
-#define CPU_FTRS_44X   (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
-#define CPU_FTRS_440x6 (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
+#define CPU_FTRS_40X   (CPU_FTR_NOEXECUTE)
+#define CPU_FTRS_44X   (CPU_FTR_NOEXECUTE)
+#define CPU_FTRS_440x6 (CPU_FTR_NOEXECUTE | \
            CPU_FTR_INDEXED_DCR)
 #define CPU_FTRS_47X   (CPU_FTRS_440x6)
 #define CPU_FTRS_E200  (CPU_FTR_SPE_COMP | \
-           CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
+           CPU_FTR_COHERENT_ICACHE | \
            CPU_FTR_NOEXECUTE | \
            CPU_FTR_DEBUG_LVL_EXC)
 #define CPU_FTRS_E500  (CPU_FTR_MAYBE_CAN_DOZE | \
-           CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
+           CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
            CPU_FTR_NOEXECUTE)
 #define CPU_FTRS_E500_2        (CPU_FTR_MAYBE_CAN_DOZE | \
            CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
-           CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
-#define CPU_FTRS_E500MC        (CPU_FTR_NODSISRALIGN | \
+           CPU_FTR_NOEXECUTE)
+#define CPU_FTRS_E500MC        ( \
            CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
            CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
 /*
  * e5500/e6500 erratum A-006958 is a timebase bug that can use the
  * same workaround as CPU_FTR_CELL_TB_BUG.
  */
-#define CPU_FTRS_E5500 (CPU_FTR_NODSISRALIGN | \
+#define CPU_FTRS_E5500 ( \
            CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
            CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
            CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG)
-#define CPU_FTRS_E6500 (CPU_FTR_NODSISRALIGN | \
+#define CPU_FTRS_E6500 ( \
            CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
            CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
            CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
@@ -552,7 +552,6 @@ enum {
 #define CPU_FTRS_DT_CPU_BASE                   \
        (CPU_FTR_LWSYNC |                       \
         CPU_FTR_FPU_UNAVAILABLE |              \
-        CPU_FTR_NODSISRALIGN |                 \
         CPU_FTR_NOEXECUTE |                    \
         CPU_FTR_COHERENT_ICACHE |              \
         CPU_FTR_STCX_CHECKS_ADDRESS |          \
index 9d07965..bd8faa2 100644 (file)
@@ -273,13 +273,6 @@ static int __init feat_enable_idle_nap(struct dt_cpu_feature *f)
        return 1;
 }
 
-static int __init feat_enable_align_dsisr(struct dt_cpu_feature *f)
-{
-       cur_cpu_spec->cpu_features &= ~CPU_FTR_NODSISRALIGN;
-
-       return 1;
-}
-
 static int __init feat_enable_idle_stop(struct dt_cpu_feature *f)
 {
        u64 lpcr;
@@ -642,7 +635,7 @@ static struct dt_cpu_feature_match __initdata
        {"tm-suspend-hypervisor-assist", feat_enable, CPU_FTR_P9_TM_HV_ASSIST},
        {"tm-suspend-xer-so-bug", feat_enable, CPU_FTR_P9_TM_XER_SO_BUG},
        {"idle-nap", feat_enable_idle_nap, 0},
-       {"alignment-interrupt-dsisr", feat_enable_align_dsisr, 0},
+       /* alignment-interrupt-dsisr ignored */
        {"idle-stop", feat_enable_idle_stop, 0},
        {"machine-check-power8", feat_enable_mce_power8, 0},
        {"performance-monitor-power8", feat_enable_pmu_power8, 0},
index c1545f2..ae3c417 100644 (file)
@@ -165,7 +165,6 @@ static struct ibm_pa_feature {
 #ifdef CONFIG_PPC_RADIX_MMU
        { .pabyte = 40, .pabit = 0, .mmu_features  = MMU_FTR_TYPE_RADIX | MMU_FTR_GTSE },
 #endif
-       { .pabyte = 1,  .pabit = 1, .invert = 1, .cpu_features = CPU_FTR_NODSISRALIGN },
        { .pabyte = 5,  .pabit = 0, .cpu_features  = CPU_FTR_REAL_LE,
                                    .cpu_user_ftrs = PPC_FEATURE_TRUE_LE },
        /*