ppc4xx: Add initial 460SX defines for the cpu/ppc4xx directory.

Signed-off-by: Feng Kan <fkan@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index a27e276..f813ba6 100644 (file)
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -52,7 +52,8 @@
 
 #if defined(CONFIG_SPD_EEPROM) &&                              \
        (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
-        defined(CONFIG_460EX) || defined(CONFIG_460GT))
+        defined(CONFIG_460EX) || defined(CONFIG_460GT)  || \
+        defined(CONFIG_460SX))
 
 /*-----------------------------------------------------------------------------+
  * Defines

diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index 39f439d..ef32bc6 100644 (file)
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -184,6 +184,19 @@ static char *bootstrap_str[] = {
 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
 #endif
 
+#if defined(CONFIG_460SX)
+#define SDR0_PINSTP_SHIFT      29
+static char *bootstrap_str[] = {
+       "EBC (8 bits)",
+       "EBC (16 bits)",
+       "EBC (32 bits)",
+       "NAND (8 bits)",
+       "I2C (Addr 0x54)",      /* A8 */
+       "I2C (Addr 0x52)",      /* A4 */
+};
+static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G' };
+#endif
+
 #if defined(CONFIG_405EZ)
 #define SDR0_PINSTP_SHIFT      28
 static char *bootstrap_str[] = {
@@ -509,6 +522,26 @@ int checkcpu (void)
                strcpy(addstr, "Security/Kasumi support");
                break;
 
+       case PVR_460SX_RA:
+               puts("SX Rev. A");
+               strcpy(addstr, "Security support");
+               break;
+
+       case PVR_460SX_RA_V1:
+               puts("SX Rev. A");
+               strcpy(addstr, "No Security support");
+               break;
+
+       case PVR_460GX_RA:
+               puts("GX Rev. A");
+               strcpy(addstr, "Security support");
+               break;
+
+       case PVR_460GX_RA_V1:
+               puts("GX Rev. A");
+               strcpy(addstr, "No Security support");
+               break;
+
        default:
                printf (" UNKNOWN (PVR=%08x)", pvr);
                break;

diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c
index 34bd721..b86b6de 100644 (file)
--- a/cpu/ppc4xx/speed.c
+++ b/cpu/ppc4xx/speed.c
@@ -205,7 +205,8 @@ ulong get_PCI_freq (void)
 
 #elif defined(CONFIG_440)
 
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_460SX)
 static u8 pll_fwdv_multi_bits[] = {
        /* values for:  1 - 16 */
        0x00, 0x01, 0x0f, 0x04, 0x09, 0x0a, 0x0d, 0x0e, 0x03, 0x0c,

diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 426bf3c..97411bd 100644 (file)
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -677,7 +677,8 @@ _start:
        /* not all PPC's have internal SRAM usable as L2-cache */
 #if defined(CONFIG_440GX) || \
     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_460SX)
        mtdcr   l2_cache_cfg,r0         /* Ensure L2 Cache is off */
 #endif
 
@@ -720,6 +721,19 @@ _start:
        lis     r1,0x4000               /* BAS = 8000_0000 */
        ori     r1,r1,0x4580            /* 16k */
        mtdcr   isram0_sb0cr,r1
+#elif defined(CONFIG_460SX)
+       lis     r1,0x0000               /* BAS = 0000_0000 */
+       ori     r1,r1,0x0B84            /* first 128k */
+       mtdcr   isram0_sb0cr,r1
+       lis     r1,0x0001
+       ori     r1,r1,0x0B84            /* second 128k */
+       mtdcr   isram0_sb1cr,r1
+       lis     r1, 0x0002
+       ori     r1,r1, 0x0B84           /* third 128k */
+       mtdcr   isram0_sb2cr,r1
+       lis     r1, 0x0003
+       ori     r1,r1, 0x0B84           /* fourth 128k */
+       mtdcr   isram0_sb3cr,r1
 #elif defined(CONFIG_440GP)
        ori     r1,r1,0x0380            /* 8k rw */
        mtdcr   isram0_sb0cr,r1
@@ -1415,7 +1429,8 @@ relocate_code:
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_460SX)
        /*
         * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
         * to speed up the boot process. Now this cache needs to be disabled.