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[AMDGPU] UBSan bug fix for r345710
author
Neil Henning
<neil.henning@amd.com>
Fri, 2 Nov 2018 10:24:57 +0000
(10:24 +0000)
committer
Neil Henning
<neil.henning@amd.com>
Fri, 2 Nov 2018 10:24:57 +0000
(10:24 +0000)
UBSan detected an error in our ISelLowering that is exposed only when
you have a dmask == 0x1. Fix this by adding in an explicit check to
ensure we don't do the UBSan detected shl << 32.
llvm-svn: 345962
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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diff --git
a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index
66eb9bb
..
55b1a87
100644
(file)
--- a/
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@
-8799,7
+8799,7
@@
SDNode *SITargetLowering::adjustWritemask(MachineSDNode *&Node,
// Set which texture component corresponds to the lane.
unsigned Comp;
- for (unsigned i = 0, Dmask = OldDmask;
i <= Lane
; i++) {
+ for (unsigned i = 0, Dmask = OldDmask;
(i <= Lane) && (Dmask != 0)
; i++) {
Comp = countTrailingZeros(Dmask);
Dmask &= ~(1 << Comp);
}