unsigned NumOps = Ops.size();
switch (Op0.getOpcode()) {
+ case X86ISD::VBROADCAST: {
+ if (!IsSplat && VT == MVT::v4f64 && llvm::all_of(Ops, [Op0](SDValue Op) {
+ return Op.getOperand(0).getValueType().is128BitVector();
+ }))
+ return DAG.getNode(X86ISD::MOVDDUP, DL, VT,
+ ConcatSubOperand(VT, Ops, 0));
+ break;
+ }
+ case X86ISD::MOVDDUP: {
+ if (!IsSplat)
+ return DAG.getNode(Op0.getOpcode(), DL, VT,
+ ConcatSubOperand(VT, Ops, 0));
+ break;
+ }
case X86ISD::SHUFP: {
// Add SHUFPD support if/when necessary.
if (!IsSplat && VT.getScalarType() == MVT::f32 &&
define <4 x double> @shuffle_v4f64_0044_v2f64(<2 x double> %a, <2 x double> %b) {
; ALL-LABEL: shuffle_v4f64_0044_v2f64:
; ALL: # %bb.0:
-; ALL-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
-; ALL-NEXT: vmovddup {{.*#+}} xmm1 = xmm1[0,0]
+; ALL-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
; ALL-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; ALL-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
; ALL-NEXT: retq
%1 = shufflevector <2 x double> %a, <2 x double> undef, <2 x i32> <i32 0, i32 0>
%2 = shufflevector <2 x double> %b, <2 x double> undef, <2 x i32> <i32 0, i32 0>