OUT_BATCH(primitive | R200_VF_PRIM_WALK_LIST | R200_VF_COLOR_ORDER_RGBA |
(vertex_nr << R200_VF_VERTEX_NUMBER_SHIFT));
END_BATCH();
-#if 0
- cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, VBUF_BUFSZ,
- __FUNCTION__ );
- cmd[0].i = 0;
- cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP;
- cmd[1].i = R200_CP_CMD_3D_DRAW_VBUF_2;
- cmd[2].i = (primitive |
- R200_VF_PRIM_WALK_LIST |
- R200_VF_COLOR_ORDER_RGBA |
- (vertex_nr << R200_VF_VERTEX_NUMBER_SHIFT));
-#endif
}
+static void r200FireEB(r200ContextPtr rmesa, int vertex_count, int type)
+{
+ BATCH_LOCALS(&rmesa->radeon);
+
+ if (vertex_count > 0) {
+ BEGIN_BATCH(8);
+ OUT_BATCH_PACKET3(R200_CP_CMD_3D_DRAW_INDX_2, 0);
+ OUT_BATCH(R200_VF_PRIM_WALK_IND |
+ ((vertex_count + 0) << 16) |
+ type);
+
+ if (!rmesa->radeon.radeonScreen->kernel_mm) {
+ OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2);
+ OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810);
+ OUT_BATCH_RELOC(rmesa->tcl.elt_dma_offset,
+ rmesa->tcl.elt_dma_bo,
+ rmesa->tcl.elt_dma_offset,
+ RADEON_GEM_DOMAIN_GTT, 0, 0);
+ OUT_BATCH(vertex_count/2);
+ } else {
+ OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2);
+ OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810);
+ OUT_BATCH(rmesa->tcl.elt_dma_offset);
+ OUT_BATCH(vertex_count/2);
+ radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
+ rmesa->tcl.elt_dma_bo,
+ RADEON_GEM_DOMAIN_GTT, 0, 0);
+ }
+ END_BATCH();
+ }
+}
-void r200FlushElts( GLcontext *ctx )
+void r200FlushElts( r200ContextPtr rmesa )
{
- r200ContextPtr rmesa = R200_CONTEXT(ctx);
- int *cmd = (int *)(rmesa->store.cmd_buf + rmesa->store.elts_start);
int dwords;
- int nr = (rmesa->store.cmd_used - (rmesa->store.elts_start + 12)) / 2;
+ int nr, elt_used = rmesa->tcl.elt_used;
if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS))
- fprintf(stderr, "%s\n", __FUNCTION__);
+ fprintf(stderr, "%s %x %d\n", __FUNCTION__, rmesa->tcl.hw_primitive, elt_used);
- assert( rmesa->dma.flush == r200FlushElts );
- rmesa->dma.flush = NULL;
+ assert( rmesa->tcl.flush == r200FlushElts );
+ rmesa->tcl.flush = NULL;
- /* Cope with odd number of elts:
- */
- rmesa->store.cmd_used = (rmesa->store.cmd_used + 2) & ~2;
- dwords = (rmesa->store.cmd_used - rmesa->store.elts_start) / 4;
+ elt_used = (elt_used + 2) & ~2;
- cmd[1] |= (dwords - 3) << 16;
- cmd[2] |= nr << R200_VF_VERTEX_NUMBER_SHIFT;
+ nr = elt_used / 2;
+
+ radeon_bo_unmap(rmesa->tcl.elt_dma_bo);
+
+ r200FireEB(rmesa, nr, rmesa->tcl.hw_primitive);
+
+ radeon_bo_unref(rmesa->tcl.elt_dma_bo);
+ rmesa->tcl.elt_dma_bo = NULL;
if (R200_DEBUG & DEBUG_SYNC) {
fprintf(stderr, "%s: Syncing\n", __FUNCTION__);
GLuint primitive,
GLuint min_nr )
{
- drm_radeon_cmd_header_t *cmd;
GLushort *retval;
if (R200_DEBUG & DEBUG_IOCTL)
assert((primitive & R200_VF_PRIM_WALK_IND));
r200EmitState( rmesa );
-
- // cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, ELTS_BUFSZ(min_nr),
- // __FUNCTION__ );
- cmd[0].i = 0;
- cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP;
- cmd[1].i = R200_CP_CMD_3D_DRAW_INDX_2;
- cmd[2].i = (primitive |
- R200_VF_PRIM_WALK_IND |
- R200_VF_COLOR_ORDER_RGBA);
+ rmesa->tcl.elt_dma_bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom,
+ 0, R200_ELT_BUF_SZ, 4,
+ RADEON_GEM_DOMAIN_GTT, 0);
+ rmesa->tcl.elt_dma_offset = 0;
+ rmesa->tcl.elt_used = min_nr * 2;
+
+ radeon_bo_map(rmesa->tcl.elt_dma_bo, 1);
+ retval = rmesa->tcl.elt_dma_bo->ptr + rmesa->tcl.elt_dma_offset;
- retval = (GLushort *)(cmd+3);
if (R200_DEBUG & DEBUG_PRIMS)
- fprintf(stderr, "%s: header 0x%x prim %x \n",
- __FUNCTION__,
- cmd[1].i, primitive);
+ fprintf(stderr, "%s: header prim %x \n",
+ __FUNCTION__, primitive);
- assert(!rmesa->dma.flush);
+ assert(!rmesa->tcl.flush);
rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
- rmesa->dma.flush = r200FlushElts;
-
- rmesa->store.elts_start = ((char *)cmd) - rmesa->store.cmd_buf;
+ rmesa->tcl.flush = r200FlushElts;
return retval;
}
}
END_BATCH();
}
-
-#if 0
-void r200EmitAOS( r200ContextPtr rmesa,
- struct radeon_dma_region **component,
- GLuint nr,
- GLuint offset )
-{
- drm_radeon_cmd_header_t *cmd;
- int sz = AOS_BUFSZ(nr);
- int i;
- int *tmp;
- if (R200_DEBUG & DEBUG_IOCTL)
- fprintf(stderr, "%s nr arrays: %d\n", __FUNCTION__, nr);
-
- cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, sz, __FUNCTION__ );
- cmd[0].i = 0;
- cmd[0].header.cmd_type = RADEON_CMD_PACKET3;
- cmd[1].i = R200_CP_CMD_3D_LOAD_VBPNTR | (((sz / sizeof(int)) - 3) << 16);
- cmd[2].i = nr;
- tmp = &cmd[0].i;
- cmd += 3;
-
- for (i = 0 ; i < nr ; i++) {
- if (i & 1) {
- cmd[0].i |= ((component[i]->aos_stride << 24) |
- (component[i]->aos_size << 16));
- cmd[2].i = (component[i]->aos_start +
- offset * component[i]->aos_stride * 4);
- cmd += 3;
- }
- else {
- cmd[0].i = ((component[i]->aos_stride << 8) |
- (component[i]->aos_size << 0));
- cmd[1].i = (component[i]->aos_start +
- offset * component[i]->aos_stride * 4);
- }
- }
-
- if (R200_DEBUG & DEBUG_VERTS) {
- fprintf(stderr, "%s:\n", __FUNCTION__);
- for (i = 0 ; i < sz ; i++)
- fprintf(stderr, " %d: %x\n", i, tmp[i]);
- }
-}
-#endif
-
-void r200EmitBlit( r200ContextPtr rmesa,
- GLuint color_fmt,
- GLuint src_pitch,
- GLuint src_offset,
- GLuint dst_pitch,
- GLuint dst_offset,
- GLint srcx, GLint srcy,
- GLint dstx, GLint dsty,
- GLuint w, GLuint h )
+void r200FireAOS(r200ContextPtr rmesa, int vertex_count, int type)
{
- drm_radeon_cmd_header_t *cmd;
+ BATCH_LOCALS(&rmesa->radeon);
- if (R200_DEBUG & DEBUG_IOCTL)
- fprintf(stderr, "%s src %x/%x %d,%d dst: %x/%x %d,%d sz: %dx%d\n",
- __FUNCTION__,
- src_pitch, src_offset, srcx, srcy,
- dst_pitch, dst_offset, dstx, dsty,
- w, h);
-
- assert( (src_pitch & 63) == 0 );
- assert( (dst_pitch & 63) == 0 );
- assert( (src_offset & 1023) == 0 );
- assert( (dst_offset & 1023) == 0 );
- assert( w < (1<<16) );
- assert( h < (1<<16) );
-
- // cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, 8 * sizeof(int),
- // __FUNCTION__ );
-
-
- cmd[0].header.cmd_type = RADEON_CMD_PACKET3;
- cmd[1].i = R200_CP_CMD_BITBLT_MULTI | (5 << 16);
- cmd[2].i = (RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
- RADEON_GMC_DST_PITCH_OFFSET_CNTL |
- RADEON_GMC_BRUSH_NONE |
- (color_fmt << 8) |
- RADEON_GMC_SRC_DATATYPE_COLOR |
- RADEON_ROP3_S |
- RADEON_DP_SRC_SOURCE_MEMORY |
- RADEON_GMC_CLR_CMP_CNTL_DIS |
- RADEON_GMC_WR_MSK_DIS );
-
- cmd[3].i = ((src_pitch/64)<<22) | (src_offset >> 10);
- cmd[4].i = ((dst_pitch/64)<<22) | (dst_offset >> 10);
- cmd[5].i = (srcx << 16) | srcy;
- cmd[6].i = (dstx << 16) | dsty; /* dst */
- cmd[7].i = (w << 16) | h;
+ BEGIN_BATCH(3);
+ OUT_BATCH_PACKET3(R200_CP_CMD_3D_DRAW_VBUF_2, 0);
+ OUT_BATCH(R200_VF_PRIM_WALK_LIST | (vertex_count << 16) | type);
+ END_BATCH();
}
-
-void r200EmitWait( r200ContextPtr rmesa, GLuint flags )
-{
- drm_radeon_cmd_header_t *cmd;
-
- assert( !(flags & ~(RADEON_WAIT_2D|RADEON_WAIT_3D)) );
-
- // cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, 1 * sizeof(int),
- // __FUNCTION__ );
- cmd[0].i = 0;
- cmd[0].wait.cmd_type = RADEON_CMD_WAIT;
- cmd[0].wait.flags = flags;
-}
#define R200_CMD_BUF_SZ (16*1024)
-
+#define R200_ELT_BUF_SZ (16*1024)
/* r200_tcl.c
*/
struct r200_tcl_info {
GLuint *Elts;
+ struct radeon_bo *elt_dma_bo;
+ int elt_dma_offset; /** Offset into this buffer object, in bytes */
+ int elt_used;
+
+ void (*flush) (r200ContextPtr);
struct radeon_dma_region vertex_data[15];
};
rmesa->store = saved_store;
}
-#if 0
-int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller )
-{
- int ret, i;
- drm_radeon_cmd_buffer_t cmd;
-
- if (rmesa->radeon.lost_context)
- r200BackUpAndEmitLostStateLocked( rmesa );
-
- if (R200_DEBUG & DEBUG_IOCTL) {
- fprintf(stderr, "%s from %s\n", __FUNCTION__, caller);
-
- if (0 & R200_DEBUG & DEBUG_VERBOSE)
- for (i = 0 ; i < rmesa->store.cmd_used ; i += 4 )
- fprintf(stderr, "%d: %x\n", i/4,
- *(int *)(&rmesa->store.cmd_buf[i]));
- }
-
- if (R200_DEBUG & DEBUG_DMA)
- fprintf(stderr, "%s: Releasing %d buffers\n", __FUNCTION__,
- rmesa->dma.nr_released_bufs);
-
-
- if (R200_DEBUG & DEBUG_SANITY) {
- if (rmesa->radeon.state.scissor.enabled)
- ret = r200SanityCmdBuffer( rmesa,
- rmesa->radeon.state.scissor.numClipRects,
- rmesa->radeon.state.scissor.pClipRects);
- else
- ret = r200SanityCmdBuffer( rmesa,
- rmesa->radeon.numClipRects,
- rmesa->radeon.pClipRects);
- if (ret) {
- fprintf(stderr, "drmSanityCommandWrite: %d\n", ret);
- goto out;
- }
- }
-
-
- if (R200_DEBUG & DEBUG_MEMORY) {
- if (! driValidateTextureHeaps( rmesa->radeon.texture_heaps, rmesa->radeon.nr_heaps,
- & rmesa->radeon.swapped ) ) {
- fprintf( stderr, "%s: texture memory is inconsistent - expect "
- "mangled textures\n", __FUNCTION__ );
- }
- }
-
-
- cmd.bufsz = rmesa->store.cmd_used;
- cmd.buf = rmesa->store.cmd_buf;
-
- if (rmesa->radeon.state.scissor.enabled) {
- cmd.nbox = rmesa->radeon.state.scissor.numClipRects;
- cmd.boxes = (drm_clip_rect_t *)rmesa->radeon.state.scissor.pClipRects;
- } else {
- cmd.nbox = rmesa->radeon.numClipRects;
- cmd.boxes = (drm_clip_rect_t *)rmesa->radeon.pClipRects;
- }
-
- ret = drmCommandWrite( rmesa->radeon.dri.fd,
- DRM_RADEON_CMDBUF,
- &cmd, sizeof(cmd) );
-
- if (ret)
- fprintf(stderr, "drmCommandWrite: %d\n", ret);
-
- if (R200_DEBUG & DEBUG_SYNC) {
- fprintf(stderr, "\nSyncing in %s\n\n", __FUNCTION__);
- radeonWaitForIdleLocked( &rmesa->radeon );
- }
-
-
- out:
- rmesa->store.primnr = 0;
- rmesa->store.statenr = 0;
- rmesa->store.cmd_used = 0;
- rmesa->dma.nr_released_bufs = 0;
- rmesa->save_on_next_emit = 1;
-
- return ret;
-}
-
-/* Note: does not emit any commands to avoid recursion on
- * r200AllocCmdBuf.
- */
-void r200FlushCmdBuf( r200ContextPtr rmesa, const char *caller )
-{
- int ret;
-
- LOCK_HARDWARE( &rmesa->radeon );
-
- ret = rcommonFlushCmdBufLocked( rmesa, caller );
-
- UNLOCK_HARDWARE( &rmesa->radeon );
-
- if (ret) {
- fprintf(stderr, "drmRadeonCmdBuffer: %d (exiting)\n", ret);
- exit(ret);
- }
-}
-#endif
-
-
-/* =============================================================
- * Hardware vertex buffer handling
- */
-
-#if 0
-void r200RefillCurrentDmaRegion( r200ContextPtr rmesa )
-{
- struct radeon_dma_buffer *dmabuf;
- int fd = rmesa->radeon.dri.fd;
- int index = 0;
- int size = 0;
- drmDMAReq dma;
- int ret;
-
- if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_DMA))
- fprintf(stderr, "%s\n", __FUNCTION__);
-
- if (rmesa->dma.flush) {
- rmesa->dma.flush( rmesa->radeon.glCtx );
- }
-
- if (rmesa->dma.current.buf)
- r200ReleaseDmaRegion( rmesa, &rmesa->dma.current, __FUNCTION__ );
-
- if (rmesa->dma.nr_released_bufs > 4)
- rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ );
-
- dma.context = rmesa->radeon.dri.hwContext;
- dma.send_count = 0;
- dma.send_list = NULL;
- dma.send_sizes = NULL;
- dma.flags = 0;
- dma.request_count = 1;
- dma.request_size = RADEON_BUFFER_SIZE;
- dma.request_list = &index;
- dma.request_sizes = &size;
- dma.granted_count = 0;
-
- LOCK_HARDWARE(&rmesa->radeon); /* no need to validate */
-
- while (1) {
- ret = drmDMA( fd, &dma );
- if (ret == 0)
- break;
-
- if (rmesa->dma.nr_released_bufs) {
- rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ );
- }
-
- if (rmesa->radeon.do_usleeps) {
- UNLOCK_HARDWARE( &rmesa->radeon );
- DO_USLEEP( 1 );
- LOCK_HARDWARE( &rmesa->radeon );
- }
- }
-
- UNLOCK_HARDWARE(&rmesa->radeon);
-
- if (R200_DEBUG & DEBUG_DMA)
- fprintf(stderr, "Allocated buffer %d\n", index);
-
- dmabuf = CALLOC_STRUCT( radeon_dma_buffer );
- dmabuf->buf = &rmesa->radeon.radeonScreen->buffers->list[index];
- dmabuf->refcount = 1;
-
- rmesa->dma.current.buf = dmabuf;
- rmesa->dma.current.address = dmabuf->buf->address;
- rmesa->dma.current.end = dmabuf->buf->total;
- rmesa->dma.current.start = 0;
- rmesa->dma.current.ptr = 0;
-}
-
-void r200ReleaseDmaRegion( r200ContextPtr rmesa,
- struct radeon_dma_region *region,
- const char *caller )
-{
- if (R200_DEBUG & DEBUG_IOCTL)
- fprintf(stderr, "%s from %s\n", __FUNCTION__, caller);
-
- if (!region->buf)
- return;
-
- if (rmesa->dma.flush)
- rmesa->dma.flush( rmesa->radeon.glCtx );
-
- if (--region->buf->refcount == 0) {
- drm_radeon_cmd_header_t *cmd;
-
- if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_DMA))
- fprintf(stderr, "%s -- DISCARD BUF %d\n", __FUNCTION__,
- region->buf->buf->idx);
-
- cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, sizeof(*cmd),
- __FUNCTION__ );
- cmd->dma.cmd_type = RADEON_CMD_DMA_DISCARD;
- cmd->dma.buf_idx = region->buf->buf->idx;
- FREE(region->buf);
- rmesa->dma.nr_released_bufs++;
- }
-
- region->buf = NULL;
- region->start = 0;
-}
-
-/* Allocates a region from rmesa->dma.current. If there isn't enough
- * space in current, grab a new buffer (and discard what was left of current)
- */
-void r200AllocDmaRegion( r200ContextPtr rmesa,
- struct radeon_dma_region *region,
- int bytes,
- int alignment )
-{
- if (R200_DEBUG & DEBUG_IOCTL)
- fprintf(stderr, "%s %d\n", __FUNCTION__, bytes);
-
- if (rmesa->dma.flush)
- rmesa->dma.flush( rmesa->radeon.glCtx );
-
- if (region->buf)
- r200ReleaseDmaRegion( rmesa, region, __FUNCTION__ );
-
- alignment--;
- rmesa->dma.current.start = rmesa->dma.current.ptr =
- (rmesa->dma.current.ptr + alignment) & ~alignment;
-
- if ( rmesa->dma.current.ptr + bytes > rmesa->dma.current.end )
- r200RefillCurrentDmaRegion( rmesa );
-
- region->start = rmesa->dma.current.start;
- region->ptr = rmesa->dma.current.start;
- region->end = rmesa->dma.current.start + bytes;
- region->address = rmesa->dma.current.address;
- region->buf = rmesa->dma.current.buf;
- region->buf->refcount++;
-
- rmesa->dma.current.ptr += bytes; /* bug - if alignment > 7 */
- rmesa->dma.current.start =
- rmesa->dma.current.ptr = (rmesa->dma.current.ptr + 0x7) & ~0x7;
-
- assert( rmesa->dma.current.ptr <= rmesa->dma.current.end );
-}
-#endif
-
/* ================================================================
* Buffer clear
*/
if (rmesa->dma.flush)
rmesa->dma.flush( ctx );
+ if (rmesa->tcl.flush)
+ rmesa->tcl.flush( rmesa );
+
r200EmitState( rmesa );
if (rmesa->radeon.cmdbuf.cs->cdw)
GLuint primitive,
GLuint vertex_nr );
-extern void r200FlushElts(GLcontext *ctx);
+extern void r200FlushElts(r200ContextPtr rmesa);
+
extern GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa,
GLuint primitive,
GLuint cpp = rmesa->radeon.radeonScreen->cpp;
GLint size = width * height * cpp;
+ return GL_FALSE;
+#if 0
if (R200_DEBUG & DEBUG_PIXEL)
fprintf(stderr, "%s\n", __FUNCTION__);
pitch * height * rmesa->radeon.radeonScreen->cpp ) ) {
if (R200_DEBUG & DEBUG_PIXEL)
fprintf(stderr, "%s: dest not GART\n", __FUNCTION__);
- return GL_FALSE;
}
/* Need GL_PACK_INVERT_MESA to cope with upsidedown results from
UNLOCK_HARDWARE( &rmesa->radeon );
r200Finish( ctx ); /* required by GL */
-
+#endif
return GL_TRUE;
}
if (R200_DEBUG & DEBUG_PIXEL)
fprintf(stderr, "%s\n", __FUNCTION__);
-
+#if 0
switch ( rmesa->radeon.radeonScreen->cpp ) {
case 2:
blit_format = R200_CP_COLOR_FORMAT_RGB565;
rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ );
radeonWaitForIdleLocked( &rmesa->radeon ); /* required by GL */
UNLOCK_HARDWARE( &rmesa->radeon );
+#endif
}
return GL_FALSE;
}
- if ( r200IsGartMemory(rmesa, pixels, size) )
+ if (0)// r200IsGartMemory(rmesa, pixels, size) )
{
do_draw_pix( ctx, x, y, width, height, pitch, pixels, planemask );
return GL_TRUE;
static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr )
{
- fprintf(stderr,"alloc elts\n");
- if (rmesa->dma.flush == r200FlushElts &&
- rmesa->store.cmd_used + nr*2 < R200_CMD_BUF_SZ) {
+ fprintf(stderr,"alloc elts %d %d\n", nr, rmesa->tcl.elt_used);
+ if (rmesa->tcl.flush == r200FlushElts &&
+ rmesa->tcl.elt_used + nr*2 < R200_ELT_BUF_SZ) {
- GLushort *dest = (GLushort *)(rmesa->store.cmd_buf +
- rmesa->store.cmd_used);
+ GLushort *dest = (GLushort *)(rmesa->tcl.elt_dma_bo->ptr +
+ rmesa->tcl.elt_used);
- rmesa->store.cmd_used += nr*2;
+ rmesa->tcl.elt_used += nr*2;
return dest;
}
else {
- if (rmesa->dma.flush)
- rmesa->dma.flush( rmesa->radeon.glCtx );
+ if (rmesa->tcl.flush)
+ rmesa->tcl.flush( rmesa );
- rcommonEnsureCmdBufSpace(rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) +
- rmesa->hw.max_state_size + ELTS_BUFSZ(nr) );
+ rcommonEnsureCmdBufSpace(rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components));
r200EmitAOS( rmesa,
rmesa->tcl.nr_aos_components, 0 );
projects / profile / ivi / mesa.git / commitdiff