radeon: remove microcode version

diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c
index 9bfda00..ae31e96 100644 (file)
--- a/shared-core/radeon_cp.c
+++ b/shared-core/radeon_cp.c
@@ -893,17 +893,6 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
         */
        dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
 
-       switch(init->func) {
-       case RADEON_INIT_R200_CP:
-               dev_priv->microcode_version = UCODE_R200;
-               break;
-       case RADEON_INIT_R300_CP:
-               dev_priv->microcode_version = UCODE_R300;
-               break;
-       default:
-               dev_priv->microcode_version = UCODE_R100;
-       }
-
        dev_priv->do_boxes = 0;
        dev_priv->cp_mode = init->cp_mode;
 
@@ -951,8 +940,7 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
         */
        dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
                                           (dev_priv->color_fmt << 10) |
-                                          (dev_priv->microcode_version ==
-                                           UCODE_R100 ? RADEON_ZBLOCK16 : 0));
+                                          (dev_priv->chip_family < CHIP_R200 ? RADEON_ZBLOCK16 : 0));
 
        dev_priv->depth_clear.rb3d_zstencilcntl =
            (dev_priv->depth_fmt |
@@ -1731,6 +1719,7 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
                break;
        }
 
+       dev_priv->chip_family = flags & RADEON_FAMILY_MASK;
        if (drm_device_is_agp(dev))
                dev_priv->flags |= RADEON_IS_AGP;
        else if (drm_device_is_pcie(dev))

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 9e7d9a9..9bd23be 100644 (file)
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -136,12 +136,6 @@ enum radeon_family {
        CHIP_LAST,
 };
 
-enum radeon_cp_microcode_version {
-       UCODE_R100,
-       UCODE_R200,
-       UCODE_R300,
-};
-
 /*
  * Chip flags
  */
@@ -249,8 +243,6 @@ typedef struct drm_radeon_private {
 
        int usec_timeout;
 
-       int microcode_version;
-
        struct {
                u32 boxes;
                int freelist_timeouts;
@@ -321,6 +313,7 @@ typedef struct drm_radeon_private {
 
        int num_gb_pipes;
        int track_flush;
+       uint32_t chip_family; /* extract from flags */
 } drm_radeon_private_t;
 
 typedef struct drm_radeon_buf_priv {

diff --git a/shared-core/radeon_state.c b/shared-core/radeon_state.c
index c50ac24..57e3a3b 100644 (file)
--- a/shared-core/radeon_state.c
+++ b/shared-core/radeon_state.c
@@ -305,8 +305,9 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t *
        case RADEON_CP_3D_DRAW_INDX_2:
        case RADEON_3D_CLEAR_HIZ:
                /* safe but r200 only */
-               if (dev_priv->microcode_version != UCODE_R200) {
-                       DRM_ERROR("Invalid 3d packet for r100-class chip\n");
+               if ((dev_priv->chip_family < CHIP_R200) ||
+                   (dev_priv->chip_family > CHIP_RV280)) {
+                       DRM_ERROR("Invalid 3d packet for non r200-class chip\n");
                        return -EINVAL;
                }
                break;
@@ -359,8 +360,8 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t *
                break;
 
        case RADEON_3D_RNDR_GEN_INDX_PRIM:
-               if (dev_priv->microcode_version != UCODE_R100) {
-                       DRM_ERROR("Invalid 3d packet for r200-class chip\n");
+               if (dev_priv->chip_family > CHIP_RS200) {
+                       DRM_ERROR("Invalid 3d packet for non-r100-class chip\n");
                        return -EINVAL;
                }
                if (radeon_check_and_fixup_offset(dev_priv, file_priv, &cmd[1])) {
@@ -370,8 +371,10 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t *
                break;
 
        case RADEON_CP_INDX_BUFFER:
-               if (dev_priv->microcode_version != UCODE_R200) {
-                       DRM_ERROR("Invalid 3d packet for r100-class chip\n");
+               /* safe but r200 only */
+               if ((dev_priv->chip_family < CHIP_R200) ||
+                   (dev_priv->chip_family > CHIP_RV280)) {
+                       DRM_ERROR("Invalid 3d packet for non-r200-class chip\n");
                        return -EINVAL;
                }
                if ((cmd[1] & 0x8000ffff) != 0x80000810) {
@@ -1015,7 +1018,7 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
                        int tileoffset, nrtilesx, nrtilesy, j;
                        /* it looks like r200 needs rv-style clears, at least if hierz is not enabled? */
                        if ((dev_priv->flags & RADEON_HAS_HIERZ)
-                           && !(dev_priv->microcode_version == UCODE_R200)) {
+                           && (dev_priv->chip_family < CHIP_R200)) {
                                /* FIXME : figure this out for r200 (when hierz is enabled). Or
                                   maybe r200 actually doesn't need to put the low-res z value into
                                   the tile cache like r100, but just needs to clear the hi-level z-buffer?
@@ -1044,7 +1047,8 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
                                        ADVANCE_RING();
                                        tileoffset += depthpixperline >> 6;
                                }
-                       } else if (dev_priv->microcode_version == UCODE_R200) {
+                       } else if ((dev_priv->chip_family >= CHIP_R200) &&
+                                  (dev_priv->chip_family <= CHIP_RV280)) {
                                /* works for rv250. */
                                /* find first macro tile (8x2 4x4 z-pixels on rv250) */
                                tileoffset =
@@ -1099,7 +1103,8 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
 
                /* TODO don't always clear all hi-level z tiles */
                if ((dev_priv->flags & RADEON_HAS_HIERZ)
-                   && (dev_priv->microcode_version == UCODE_R200)
+                   && ((dev_priv->chip_family >= CHIP_R200) &&
+                       (dev_priv->chip_family <= CHIP_RV280))
                    && (flags & RADEON_USE_HIERZ))
                        /* r100 and cards without hierarchical z-buffer have no high-level z-buffer */
                        /* FIXME : the mask supposedly contains low-res z values. So can't set
@@ -1119,8 +1124,9 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
         * rendering a quad into just those buffers.  Thus, we have to
         * make sure the 3D engine is configured correctly.
         */
-       else if ((dev_priv->microcode_version == UCODE_R200) &&
-               (flags & (RADEON_DEPTH | RADEON_STENCIL))) {
+       else if ((dev_priv->chip_family >= CHIP_R200) &&
+                (dev_priv->chip_family <= CHIP_RV280) &&
+                (flags & (RADEON_DEPTH | RADEON_STENCIL))) {
 
                int tempPP_CNTL;
                int tempRE_CNTL;
@@ -2889,7 +2895,7 @@ static int radeon_cp_cmdbuf(struct drm_device *dev, void *data, struct drm_file
 
        orig_nbox = cmdbuf->nbox;
 
-       if (dev_priv->microcode_version == UCODE_R300) {
+       if (dev_priv->chip_family >= CHIP_R300) {
                int temp;
                temp = r300_do_cp_cmdbuf(dev, file_priv, cmdbuf);