dts: r64: add sata- and asm_sel nodes

asm_sel is for switching between sata and pcie mode
on r64 there is GPIO90 connected to ASM1480 which
switches RX/TX pairs to PCIe/SATA connector
output-low means sata-controller is active

with 2020-10 now reg is also needed for the phy itself

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>

diff --git a/arch/arm/dts/mt7622-bpi-r64.dts b/arch/arm/dts/mt7622-bpi-r64.dts
index c89e816..51287ce 100644 (file)
--- a/arch/arm/dts/mt7622-bpi-r64.dts
+++ b/arch/arm/dts/mt7622-bpi-r64.dts
@@ -235,3 +235,12 @@
                full-duplex;
        };
 };
+
+&gpio {
+       /*gpio 90 for setting mode to sata*/
+       asm_sel {
+               gpio-hog;
+               gpios = <90 GPIO_ACTIVE_HIGH>;
+               output-low;
+       };
+};

diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi
index fec0716..c43ad65 100644 (file)
--- a/arch/arm/dts/mt7622.dtsi
+++ b/arch/arm/dts/mt7622.dtsi
@@ -10,6 +10,7 @@
 #include <dt-bindings/power/mt7629-power.h>
 #include <dt-bindings/reset/mt7629-reset.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
 
 / {
        compatible = "mediatek,mt7622";
@@ -270,6 +271,37 @@
                };
        };
 
+       sata: sata@1a200000 {
+               compatible = "mediatek,mtk-ahci";
+               reg = <0x1a200000 0x1100>;
+               resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
+                       <&pciesys MT7622_SATA_PHY_SW_RST>,
+                       <&pciesys MT7622_SATA_PHY_REG_RST>;
+               reset-names = "axi", "sw", "reg";
+               mediatek,phy-mode = <&pciesys>;
+               ports-implemented = <0x1>;
+               phys = <&sata_port PHY_TYPE_SATA>;
+               phy-names = "sata-phy";
+               status = "okay";
+       };
+
+       sata_phy: sata-phy@1a243000 {
+               compatible = "mediatek,generic-tphy-v1";
+               reg = <0x1a243000 0x0100>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+               status = "okay";
+
+               sata_port: sata-phy@1a243000 {
+                       reg = <0x1a243000 0x0100>;
+                       clocks = <&topckgen CLK_TOP_ETH_500M>;
+                       clock-names = "ref";
+                       #phy-cells = <1>;
+                       status = "okay";
+               };
+       };
+
        ethsys: syscon@1b000000 {
                compatible = "mediatek,mt7622-ethsys", "syscon";
                reg = <0x1b000000 0x1000>;