unsigned src[3];
unsigned dest;
- /* Swizzle for the conditional for a csel */
- unsigned csel_swizzle;
+ /* Swizzle for the conditional for a csel/branch */
+ unsigned cond_swizzle;
/* Special fields for an ALU instruction */
midgard_reg_info registers;
};
if (nr_inputs == 3) {
- ins.csel_swizzle = SWIZZLE_FROM_ARRAY(nirmods[2]->swizzle);
+ ins.cond_swizzle = SWIZZLE_FROM_ARRAY(nirmods[2]->swizzle);
assert(!nirmods[2]->abs);
assert(!nirmods[2]->negate);
}
mir_get_swizzle(midgard_instruction *ins, unsigned idx)
{
if (ins->type == TAG_ALU_4) {
- if (idx == 2)
- return ins->csel_swizzle;
+ if (idx == 2 || ins->compact_branch)
+ return ins->cond_swizzle;
unsigned b = (idx == 0) ? ins->alu.src1 : ins->alu.src2;
mir_set_swizzle(midgard_instruction *ins, unsigned idx, unsigned new)
{
if (ins->type == TAG_ALU_4) {
+ if (idx == 2 || ins->compact_branch) {
+ ins->cond_swizzle = new;
+ return;
+ }
+
unsigned b = (idx == 0) ? ins->alu.src1 : ins->alu.src2;
midgard_vector_alu_src s =