ARM: dts: exynos5420: change speed and parent of NoC clock

This patch changes speed to 400MHz and parent clock of NoC bus.
The old parent, which was set by bootloader, had speed 533MHz.
When the exynos-bus driver tried to change the frequency to 400MHz,
in low level the clock divider set val 2 and the actual frequency of
the bus was 266MHz. For the rest OPPs the same situation apply.
Having the right parent, meaning: PLL ratios declared and possible divider
values equal the OPPs values, if crucial for the buses.

This bus is used for data transport between GPU and DRAM. The performance
can be checked by fixing the freq of the bus (not by the ondemand governor)
and fixing the freq of GPU, then running some openGL benchmarks.

Change-Id: Ied8d9f50c7444a809670234ff62dc409f1f42a5f
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>

diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index e67b59e..61f52ef 100644 (file)
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -45,6 +45,9 @@
                        <&nocp_mem1_0>, <&nocp_mem1_1>;
        vdd-supply = <&buck3_reg>;
        exynos,saturation-ratio = <100>;
+       assigned-clocks = <&clock CLK_MOUT_WCORE>;
+       assigned-clock-parents = <&clock CLK_FF_DOUT_SPLL2>;
+       assigned-clock-rates = <400000000>;
        status = "okay";
 };