ram: rockchip: update lpddr4 timing for rk3399
authorKever Yang <kever.yang@rock-chips.com>
Fri, 15 Nov 2019 03:04:50 +0000 (11:04 +0800)
committerKever Yang <kever.yang@rock-chips.com>
Sun, 17 Nov 2019 08:23:56 +0000 (16:23 +0800)
Update lpddr timing in lpddr4-400 and lpddr4-800 file from rockchip
vendor code;

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc
drivers/ram/rockchip/sdram-rk3399-lpddr4-800.inc

index 6ddc01c..209ef57 100644 (file)
                        },
                        {
                                .ddrtiminga0 = {
-                                       0x80241d22,
+                                       0x8010100d,
                                },
                                .ddrtimingb0 = {
-                                       0x15050f08,
+                                       0x08020b04,
                                },
                                .ddrtimingc0 = {
                                        0x00000602,
                                },
                                .devtodev0 = {
-                                       0x00002122,
+                                       0x00002562,
                                },
                                .ddrmode = {
                                        0x0000004c,
                        },
                        {
                                .ddrtiminga0 = {
-                                       0x80241d22,
+                                       0x8010100d,
                                },
                                .ddrtimingb0 = {
-                                       0x15050f08,
+                                       0x08020b04,
                                },
                                .ddrtimingc0 = {
                                        0x00000602,
                                },
                                .devtodev0 = {
-                                       0x00002122,
+                                       0x00002562,
                                },
                                .ddrmode = {
                                        0x0000004c,
index 307f6ee..7d11b4c 100644 (file)
                        },
                        {
                                .ddrtiminga0 = {
-                                       0x80241d22,
+                                       0x801c1819,
                                },
                                .ddrtimingb0 = {
-                                       0x15050f08,
+                                       0x10040c05,
                                },
                                .ddrtimingc0 = {
                                        0x00000602,
                                },
                                .devtodev0 = {
-                                       0x00002122,
+                                       0x00002672,
                                },
                                .ddrmode = {
                                        0x0000004c,