intel/compiler: In XeHP prefer <1;1,0> regions before compacting

Ken performed some tests with shader-db to evaluate the effects

```
Across all 145,848 shaders generated, the results were:

Total bytes compacted before: 3,326,224
Total bytes compacted after: 60,963,280
```

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15399>

diff --git a/src/intel/compiler/brw_eu_compact.c b/src/intel/compiler/brw_eu_compact.c
index 38c9279..73fdbf5 100644 (file)
--- a/src/intel/compiler/brw_eu_compact.c
+++ b/src/intel/compiler/brw_eu_compact.c
@@ -1698,6 +1698,30 @@ has_immediate(const struct intel_device_info *devinfo, const brw_inst *inst,
 static brw_inst
 precompact(const struct intel_device_info *devinfo, brw_inst inst)
 {
+   /* In XeHP the compaction tables removed the entries for source regions
+    * <8;8,1> giving preference to <1;1,0> as the way to indicate
+    * sequential elements, so convert to those before compacting.
+    */
+   if (devinfo->verx10 >= 125) {
+      if (brw_inst_src0_reg_file(devinfo, &inst) == BRW_GENERAL_REGISTER_FILE &&
+          brw_inst_src0_vstride(devinfo, &inst) > BRW_VERTICAL_STRIDE_1 &&
+          brw_inst_src0_vstride(devinfo, &inst) == (brw_inst_src0_width(devinfo, &inst) + 1) &&
+          brw_inst_src0_hstride(devinfo, &inst) == BRW_HORIZONTAL_STRIDE_1) {
+         brw_inst_set_src0_vstride(devinfo, &inst, BRW_VERTICAL_STRIDE_1);
+         brw_inst_set_src0_width(devinfo, &inst, BRW_WIDTH_1);
+         brw_inst_set_src0_hstride(devinfo, &inst, BRW_HORIZONTAL_STRIDE_0);
+      }
+
+      if (brw_inst_src1_reg_file(devinfo, &inst) == BRW_GENERAL_REGISTER_FILE &&
+          brw_inst_src1_vstride(devinfo, &inst) > BRW_VERTICAL_STRIDE_1 &&
+          brw_inst_src1_vstride(devinfo, &inst) == (brw_inst_src1_width(devinfo, &inst) + 1) &&
+          brw_inst_src1_hstride(devinfo, &inst) == BRW_HORIZONTAL_STRIDE_1) {
+         brw_inst_set_src1_vstride(devinfo, &inst, BRW_VERTICAL_STRIDE_1);
+         brw_inst_set_src1_width(devinfo, &inst, BRW_WIDTH_1);
+         brw_inst_set_src1_hstride(devinfo, &inst, BRW_HORIZONTAL_STRIDE_0);
+      }
+   }
+
    if (brw_inst_src0_reg_file(devinfo, &inst) != BRW_IMMEDIATE_VALUE)
       return inst;