drm/amd/display: Set max vratio for prefetch to 7.9 for YUV420 MPO

[Description]
- Single 4K60 playing YUV420 MPO video blocks P-State because
  the required VRatio for prefetch is too high (luma plane for
  YUV420 is 1bpe, so swath height is 16 and prefetch requires
  more lines)
- Allow max vratio per plane to be 7.9 for single display YUV420
  MPO video cases
- Ensure that global vratio prefetch (i.e. total prefetch BW vs.
  total active bandwidth) does not excited 4.0

Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
index a09db7c..aca928e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
@@ -150,6 +150,8 @@ bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe);
 
 unsigned int dcn32_calc_num_avail_chans_for_mall(struct dc *dc, int num_chans);
 
+double dcn32_determine_max_vratio_prefetch(struct dc *dc, struct dc_state *context);
+
 /* definitions for run time init of reg offsets */
 
 /* CLK SRC */

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 27b62ef..3372ede 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -27,6 +27,7 @@
 #include "dcn32/dcn32_resource.h"
 #include "dcn20/dcn20_resource.h"
 #include "display_mode_vba_util_32.h"
+#include "dml/dcn32/display_mode_vba_32.h"
 // We need this includes for WATERMARKS_* defines
 #include "clk_mgr/dcn32/dcn32_smu13_driver_if.h"
 #include "dcn30/dcn30_resource.h"
@@ -1618,6 +1619,7 @@ bool dcn32_internal_validate_bw(struct dc *dc,
        }
 
        dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
+       context->bw_ctx.dml.soc.max_vratio_pre = dcn32_determine_max_vratio_prefetch(dc, context);
 
        if (!fast_validate)
                dcn32_full_validate_bw_helper(dc, context, pipes, &vlevel, split, merge, &pipe_cnt);
@@ -2744,3 +2746,33 @@ bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe)
        }
        return allow;
 }
+
+/**
+ * *******************************************************************************************
+ * dcn32_determine_max_vratio_prefetch: Determine max Vratio for prefetch by driver policy
+ *
+ * @param [in]: dc: Current DC state
+ * @param [in]: context: New DC state to be programmed
+ *
+ * @return: Max vratio for prefetch
+ *
+ * *******************************************************************************************
+ */
+double dcn32_determine_max_vratio_prefetch(struct dc *dc, struct dc_state *context)
+{
+       double max_vratio_pre = __DML_MAX_BW_RATIO_PRE__; // Default value is 4
+       int i;
+
+       /* For single display MPO configs, allow the max vratio to be 8
+        * if any plane is YUV420 format
+        */
+       if (context->stream_count == 1 && context->stream_status[0].plane_count > 1) {
+               for (i = 0; i < context->stream_status[0].plane_count; i++) {
+                       if (context->stream_status[0].plane_states[i]->format == SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr ||
+                                       context->stream_status[0].plane_states[i]->format == SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb) {
+                               max_vratio_pre = __DML_MAX_VRATIO_PRE__;
+                       }
+               }
+       }
+       return max_vratio_pre;
+}

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index 23e50d1..55567b9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -896,8 +896,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
                        if (v->DestinationLinesForPrefetch[k] < 2)
                                DestinationLineTimesForPrefetchLessThan2 = true;
 
-                       if (v->VRatioPrefetchY[k] > __DML_MAX_VRATIO_PRE__
-                                       || v->VRatioPrefetchC[k] > __DML_MAX_VRATIO_PRE__)
+                       if (v->VRatioPrefetchY[k] > v->MaxVRatioPre
+                                       || v->VRatioPrefetchC[k] > v->MaxVRatioPre)
                                VRatioPrefetchMoreThanMax = true;
 
                        //bool DestinationLinesToRequestVMInVBlankEqualOrMoreThan32 = false;
@@ -3397,8 +3397,8 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 
                                mode_lib->vba.VRatioInPrefetchSupported[i][j] = true;
                                for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
-                                       if (mode_lib->vba.VRatioPreY[i][j][k] > __DML_MAX_VRATIO_PRE__
-                                                       || mode_lib->vba.VRatioPreC[i][j][k] > __DML_MAX_VRATIO_PRE__
+                                       if (mode_lib->vba.VRatioPreY[i][j][k] > mode_lib->vba.MaxVRatioPre
+                                                       || mode_lib->vba.VRatioPreC[i][j][k] > mode_lib->vba.MaxVRatioPre
                                                        || mode_lib->vba.NoTimeForPrefetch[i][j][k] == true) {
                                                mode_lib->vba.VRatioInPrefetchSupported[i][j] = false;
                                        }

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h
index c8b28c8..500b3dd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h
@@ -44,7 +44,8 @@
 #define __DML_MIN_DCFCLK_FACTOR__   1.15
 
 // Prefetch schedule max vratio
-#define __DML_MAX_VRATIO_PRE__ 4.0
+#define __DML_MAX_VRATIO_PRE__ 7.9
+#define __DML_MAX_BW_RATIO_PRE__ 4.0
 
 #define __DML_VBA_MAX_DST_Y_PRE__    63.75
 

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
index 0932f49..069e9ab 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
@@ -3480,7 +3480,7 @@ bool dml32_CalculatePrefetchSchedule(
        double  prefetch_sw_bytes;
        double  bytes_pp;
        double  dep_bytes;
-       unsigned int max_vratio_pre = __DML_MAX_VRATIO_PRE__;
+       unsigned int max_vratio_pre = v->MaxVRatioPre;
        double  min_Lsw;
        double  Tsw_est1 = 0;
        double  Tsw_est3 = 0;
@@ -6150,7 +6150,9 @@ void dml32_CalculatePrefetchBandwithSupport(unsigned int NumberOfActiveSurfaces,
                bool *PrefetchBandwidthSupport)
 {
        unsigned int k;
+       double ActiveBandwidthPerSurface;
        bool NotEnoughUrgentLatencyHiding = false;
+       double TotalActiveBandwidth = 0;
        for (k = 0; k < NumberOfActiveSurfaces; ++k) {
                if (NotUrgentLatencyHiding[k]) {
                        NotEnoughUrgentLatencyHiding = true;
@@ -6159,12 +6161,16 @@ void dml32_CalculatePrefetchBandwithSupport(unsigned int NumberOfActiveSurfaces,
 
        *PrefetchBandwidth = 0;
        for (k = 0; k < NumberOfActiveSurfaces; ++k) {
+               ActiveBandwidthPerSurface = ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k] + NumberOfDPP[k] * (meta_row_bandwidth[k] + dpte_row_bandwidth[k]);
+
+               TotalActiveBandwidth += ActiveBandwidthPerSurface;
+
                *PrefetchBandwidth = *PrefetchBandwidth + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
-                               ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k] + NumberOfDPP[k] * (meta_row_bandwidth[k] + dpte_row_bandwidth[k]),
+                               ActiveBandwidthPerSurface,
                                NumberOfDPP[k] * (PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k] + PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k]) + cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]);
        }
 
-       *PrefetchBandwidthSupport = (*PrefetchBandwidth <= ReturnBW) && !NotEnoughUrgentLatencyHiding;
+       *PrefetchBandwidthSupport = (*PrefetchBandwidth <= ReturnBW) &&  (*PrefetchBandwidth <= TotalActiveBandwidth * __DML_MAX_BW_RATIO_PRE__) && !NotEnoughUrgentLatencyHiding;
        *FractionOfUrgentBandwidth = *PrefetchBandwidth / ReturnBW;
 }
 

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index 64d602e..3c07716 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -246,6 +246,7 @@ struct _vcs_dpi_soc_bounding_box_st {
        bool disable_dram_clock_change_vactive_support;
        bool allow_dram_clock_one_display_vactive;
        enum self_refresh_affinity allow_dram_self_refresh_or_dram_clock_change_in_vblank;
+       double max_vratio_pre;
 };
 
 /**

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index 8cb28b7..f9653f5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -412,6 +412,7 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib)
                soc->urgent_latency_adjustment_fabric_clock_component_us;
        mode_lib->vba.UrgentLatencyAdjustmentFabricClockReference =
                soc->urgent_latency_adjustment_fabric_clock_reference_mhz;
+       mode_lib->vba.MaxVRatioPre = soc->max_vratio_pre;
 }
 
 static void fetch_ip_params(struct display_mode_lib *mode_lib)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 876b9b5..0799374 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -263,6 +263,7 @@ struct vba_vars_st {
        int maxMpcComb;
        bool UseMaximumVStartup;
 
+       double MaxVRatioPre;
        double WritebackDISPCLK;
        double DPPCLKUsingSingleDPPLuma;
        double DPPCLKUsingSingleDPPChroma;