drm/amdgpu: rename vram_scratch into mem_scratch
authorChristian König <christian.koenig@amd.com>
Fri, 21 Jan 2022 15:59:36 +0000 (16:59 +0100)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 3 Jan 2023 21:50:03 +0000 (16:50 -0500)
Rename vram_scratch into mem_scratch and allow allocating it into GTT as
well.

The only problem with that is that we won't have a default page for the
system aperture any more.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
18 files changed:
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c
drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c
drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

index 2eef109..1d2350a 100644 (file)
@@ -608,7 +608,7 @@ int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
                                struct drm_file *filp);
 
 /* VRAM scratch page for HDP bug, default vram page */
-struct amdgpu_vram_scratch {
+struct amdgpu_mem_scratch {
        struct amdgpu_bo                *robj;
        volatile uint32_t               *ptr;
        u64                             gpu_addr;
@@ -853,7 +853,7 @@ struct amdgpu_device {
 
        /* memory management */
        struct amdgpu_mman              mman;
-       struct amdgpu_vram_scratch      vram_scratch;
+       struct amdgpu_mem_scratch       mem_scratch;
        struct amdgpu_wb                wb;
        atomic64_t                      num_bytes_moved;
        atomic64_t                      num_evictions;
index 8625af2..585e73f 100644 (file)
@@ -924,33 +924,33 @@ static int amdgpu_device_asic_init(struct amdgpu_device *adev)
 }
 
 /**
- * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page
+ * amdgpu_device_mem_scratch_init - allocate the VRAM scratch page
  *
  * @adev: amdgpu_device pointer
  *
  * Allocates a scratch page of VRAM for use by various things in the
  * driver.
  */
-static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
+static int amdgpu_device_mem_scratch_init(struct amdgpu_device *adev)
 {
-       return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
-                                      PAGE_SIZE,
-                                      AMDGPU_GEM_DOMAIN_VRAM,
-                                      &adev->vram_scratch.robj,
-                                      &adev->vram_scratch.gpu_addr,
-                                      (void **)&adev->vram_scratch.ptr);
+       return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, PAGE_SIZE,
+                                      AMDGPU_GEM_DOMAIN_VRAM |
+                                      AMDGPU_GEM_DOMAIN_GTT,
+                                      &adev->mem_scratch.robj,
+                                      &adev->mem_scratch.gpu_addr,
+                                      (void **)&adev->mem_scratch.ptr);
 }
 
 /**
- * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page
+ * amdgpu_device_mem_scratch_fini - Free the VRAM scratch page
  *
  * @adev: amdgpu_device pointer
  *
  * Frees the VRAM scratch page.
  */
-static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
+static void amdgpu_device_mem_scratch_fini(struct amdgpu_device *adev)
 {
-       amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
+       amdgpu_bo_free_kernel(&adev->mem_scratch.robj, NULL, NULL);
 }
 
 /**
@@ -2391,9 +2391,9 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
                        if (amdgpu_sriov_vf(adev))
                                amdgpu_virt_exchange_data(adev);
 
-                       r = amdgpu_device_vram_scratch_init(adev);
+                       r = amdgpu_device_mem_scratch_init(adev);
                        if (r) {
-                               DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
+                               DRM_ERROR("amdgpu_mem_scratch_init failed %d\n", r);
                                goto init_failed;
                        }
                        r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
@@ -2875,7 +2875,7 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
                        amdgpu_ucode_free_bo(adev);
                        amdgpu_free_static_csa(&adev->virt.csa_obj);
                        amdgpu_device_wb_fini(adev);
-                       amdgpu_device_vram_scratch_fini(adev);
+                       amdgpu_device_mem_scratch_fini(adev);
                        amdgpu_ib_pool_fini(adev);
                }
 
index ec4d5e1..ab2325f 100644 (file)
@@ -120,7 +120,7 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
                                max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 
                /* Set default page address. */
-               value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
+               value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
                WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
                             (u32)(value >> 12));
                WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
index 34513e8..9b3a025 100644 (file)
@@ -165,7 +165,7 @@ static void gfxhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev)
                             max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 
                /* Set default page address. */
-               value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
+               value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
                WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
                             (u32)(value >> 12));
                WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
index 3f8676d..4aacbbe 100644 (file)
@@ -167,7 +167,7 @@ static void gfxhub_v2_1_init_system_aperture_regs(struct amdgpu_device *adev)
                     max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 
        /* Set default page address. */
-       value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
+       value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
        WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
                     (u32)(value >> 12));
        WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
index 0e13370..fa42d19 100644 (file)
@@ -163,7 +163,7 @@ static void gfxhub_v3_0_init_system_aperture_regs(struct amdgpu_device *adev)
                     adev->gmc.vram_end >> 18);
 
        /* Set default page address. */
-       value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
+       value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start
                + adev->vm_manager.vram_base_offset;
        WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
                     (u32)(value >> 12));
index 080ff11..3dc17a3 100644 (file)
@@ -169,7 +169,7 @@ static void gfxhub_v3_0_3_init_system_aperture_regs(struct amdgpu_device *adev)
                     adev->gmc.vram_end >> 18);
 
        /* Set default page address. */
-       value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
+       value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start
                + adev->vm_manager.vram_base_offset;
        WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
                     (u32)(value >> 12));
index ec291d2..7f4bf2e 100644 (file)
@@ -258,7 +258,7 @@ static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
        WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
               adev->gmc.vram_end >> 12);
        WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
-              adev->vram_scratch.gpu_addr >> 12);
+              adev->mem_scratch.gpu_addr >> 12);
        WREG32(mmMC_VM_AGP_BASE, 0);
        WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
        WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
index 979da6f..b309f3a 100644 (file)
@@ -292,7 +292,7 @@ static void gmc_v7_0_mc_program(struct amdgpu_device *adev)
        WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
               adev->gmc.vram_end >> 12);
        WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
-              adev->vram_scratch.gpu_addr >> 12);
+              adev->mem_scratch.gpu_addr >> 12);
        WREG32(mmMC_VM_AGP_BASE, 0);
        WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
        WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
index 382dde1..24a256c 100644 (file)
@@ -474,7 +474,7 @@ static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
        WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
               adev->gmc.vram_end >> 12);
        WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
-              adev->vram_scratch.gpu_addr >> 12);
+              adev->mem_scratch.gpu_addr >> 12);
 
        if (amdgpu_sriov_vf(adev)) {
                tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16;
index 3e51e77..15e7cbe 100644 (file)
@@ -114,7 +114,7 @@ static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
                return;
 
        /* Set default page address. */
-       value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
+       value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
        WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
                     (u32)(value >> 12));
        WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
index 6fa7090..73afbf2 100644 (file)
@@ -134,7 +134,7 @@ static void mmhub_v1_7_init_system_aperture_regs(struct amdgpu_device *adev)
        }
 
        /* Set default page address. */
-       value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
+       value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
        WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
                     (u32)(value >> 12));
        WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
index 0e664d0..278e32d 100644 (file)
@@ -234,7 +234,7 @@ static void mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev)
        }
 
        /* Set default page address. */
-       value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
+       value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
        WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
                     (u32)(value >> 12));
        WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
index 4638ea7..fcf2813 100644 (file)
@@ -164,7 +164,7 @@ static void mmhub_v2_3_init_system_aperture_regs(struct amdgpu_device *adev)
                     max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 
        /* Set default page address. */
-       value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
+       value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
        WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
                     (u32)(value >> 12));
        WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
index 16cc822..e9dcd6f 100644 (file)
@@ -188,7 +188,7 @@ static void mmhub_v3_0_init_system_aperture_regs(struct amdgpu_device *adev)
        }
 
        /* Set default page address. */
-       value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
+       value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start +
                adev->vm_manager.vram_base_offset;
        WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
                     (u32)(value >> 12));
index 6bdf2ef..c8d478f 100644 (file)
@@ -188,7 +188,7 @@ static void mmhub_v3_0_1_init_system_aperture_regs(struct amdgpu_device *adev)
                     adev->gmc.vram_end >> 18);
 
        /* Set default page address. */
-       value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
+       value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start +
                adev->vm_manager.vram_base_offset;
        WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
                     (u32)(value >> 12));
index 45465ac..c30e40e 100644 (file)
@@ -181,7 +181,7 @@ static void mmhub_v3_0_2_init_system_aperture_regs(struct amdgpu_device *adev)
        }
 
        /* Set default page address. */
-       value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
+       value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start +
                adev->vm_manager.vram_base_offset;
        WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
                     (u32)(value >> 12));
index 445cb06..72083e9 100644 (file)
@@ -136,7 +136,7 @@ static void mmhub_v9_4_init_system_aperture_regs(struct amdgpu_device *adev,
                        max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 
                /* Set default page address. */
-               value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
+               value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
                WREG32_SOC15_OFFSET(
                        MMHUB, 0,
                        mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,