fsl,clk-source property is of type uint8 and need to be defined as
"/bits/ 8 <0>". Simply setting value to 0 raise warning:
can@2180000: fsl,clk-source:0: [0, 0, 0, 0] is too long
Signed-off-by: Kuldeep Singh <singh.kuldeep87k@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
QORIQ_CLK_PLL_DIV(8)>,
<&clockgen QORIQ_CLK_SYSCLK 0>;
clock-names = "ipg", "per";
- fsl,clk-source = <0>;
+ fsl,clk-source = /bits/ 8 <0>;
status = "disabled";
};
QORIQ_CLK_PLL_DIV(8)>,
<&clockgen QORIQ_CLK_SYSCLK 0>;
clock-names = "ipg", "per";
- fsl,clk-source = <0>;
+ fsl,clk-source = /bits/ 8 <0>;
status = "disabled";
};