rs6000.md (isa attribute): Add support for for a future processor.

2019-06-20  Michael Meissner  <meissner@linux.ibm.com>

	* config/rs6000/rs6000.md (isa attribute): Add support for
	for a future processor.

From-SVN: r272513

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d4c3220..7deb9d8 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2019-06-20  Michael Meissner  <meissner@linux.ibm.com>
+
+       * config/rs6000/rs6000.md (isa attribute): Add support for
+       for a future processor.
+
 2019-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR target/54855

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index eb03e4d..b04c705 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -267,7 +267,8 @@
   (const (symbol_ref "(enum attr_cpu) rs6000_tune")))
 
 ;; The ISA we implement.
-(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9v,p9kf,p9tf" (const_string "any"))
+(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9v,p9kf,p9tf,fut"
+  (const_string "any"))
 
 ;; Is this alternative enabled for the current CPU/ISA/etc.?
 (define_attr "enabled" ""
@@ -306,6 +307,10 @@
      (and (eq_attr "isa" "p9tf")
          (match_test "FLOAT128_VECTOR_P (TFmode)"))
      (const_int 1)
+
+     (and (eq_attr "isa" "fut")
+         (match_test "TARGET_FUTURE"))
+     (const_int 1)
     ] (const_int 0)))
 
 ;; If this instruction is microcoded on the CELL processor