drm/msm/dsi: Reduce pclk rate for compression
authorJessica Zhang <quic_jesszhan@quicinc.com>
Fri, 9 Jun 2023 22:57:14 +0000 (15:57 -0700)
committerDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Thu, 15 Jun 2023 10:08:31 +0000 (13:08 +0300)
Adjust the pclk rate to divide hdisplay by the compression ratio when DSC
is enabled.

Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/541972/
Link: https://lore.kernel.org/r/20230405-add-dsc-support-v6-2-95eab864d1b6@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
drivers/gpu/drm/msm/dsi/dsi_host.c

index a448931..98ea1da 100644 (file)
@@ -561,12 +561,27 @@ void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host)
        clk_disable_unprepare(msm_host->byte_clk);
 }
 
-static unsigned long dsi_get_pclk_rate(const struct drm_display_mode *mode, bool is_bonded_dsi)
+static unsigned long dsi_adjust_pclk_for_compression(const struct drm_display_mode *mode,
+               const struct drm_dsc_config *dsc)
+{
+       int new_hdisplay = DIV_ROUND_UP(mode->hdisplay * drm_dsc_get_bpp_int(dsc),
+                       dsc->bits_per_component * 3);
+
+       int new_htotal = mode->htotal - mode->hdisplay + new_hdisplay;
+
+       return new_htotal * mode->vtotal * drm_mode_vrefresh(mode);
+}
+
+static unsigned long dsi_get_pclk_rate(const struct drm_display_mode *mode,
+               const struct drm_dsc_config *dsc, bool is_bonded_dsi)
 {
        unsigned long pclk_rate;
 
        pclk_rate = mode->clock * 1000;
 
+       if (dsc)
+               pclk_rate = dsi_adjust_pclk_for_compression(mode, dsc);
+
        /*
         * For bonded DSI mode, the current DRM mode has the complete width of the
         * panel. Since, the complete panel is driven by two DSI controllers,
@@ -585,7 +600,7 @@ unsigned long dsi_byte_clk_get_rate(struct mipi_dsi_host *host, bool is_bonded_d
        struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
        u8 lanes = msm_host->lanes;
        u32 bpp = dsi_get_bpp(msm_host->format);
-       unsigned long pclk_rate = dsi_get_pclk_rate(mode, is_bonded_dsi);
+       unsigned long pclk_rate = dsi_get_pclk_rate(mode, msm_host->dsc, is_bonded_dsi);
        unsigned long pclk_bpp;
 
        if (lanes == 0) {
@@ -604,7 +619,7 @@ unsigned long dsi_byte_clk_get_rate(struct mipi_dsi_host *host, bool is_bonded_d
 
 static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
 {
-       msm_host->pixel_clk_rate = dsi_get_pclk_rate(msm_host->mode, is_bonded_dsi);
+       msm_host->pixel_clk_rate = dsi_get_pclk_rate(msm_host->mode, msm_host->dsc, is_bonded_dsi);
        msm_host->byte_clk_rate = dsi_byte_clk_get_rate(&msm_host->base, is_bonded_dsi,
                                                        msm_host->mode);