lcd_printf ("(C) 2008 ATMEL Corp\n");
lcd_printf ("at91support@atmel.com\n");
lcd_printf ("%s CPU at %s MHz\n",
- AT91_CPU_NAME,
+ CONFIG_SYS_AT91_CPU_NAME,
strmhz(temp, get_cpu_clk_rate()));
dram_size = 0;
lcd_printf ("(C) 2008 ATMEL Corp\n");
lcd_printf ("at91support@atmel.com\n");
lcd_printf ("%s CPU at %s MHz\n",
- AT91_CPU_NAME,
+ CONFIG_SYS_AT91_CPU_NAME,
strmhz(temp, get_cpu_clk_rate()));
dram_size = 0;
lcd_printf ("(C) 2008 ATMEL Corp\n");
lcd_printf ("at91support@atmel.com\n");
lcd_printf ("%s CPU at %s MHz\n",
- AT91_CPU_NAME,
+ CONFIG_SYS_AT91_CPU_NAME,
strmhz(temp, get_cpu_clk_rate()));
dram_size = 0;
lcd_printf ("(C) 2008 ATMEL Corp\n");
lcd_printf ("at91support@atmel.com\n");
lcd_printf ("%s CPU at %s MHz\n",
- AT91_CPU_NAME,
+ CONFIG_SYS_AT91_CPU_NAME,
strmhz(temp, get_cpu_clk_rate()));
dram_size = 0;
lcd_printf ("(C) 2008 ATMEL Corp\n");
lcd_printf ("at91support@atmel.com\n");
lcd_printf ("%s CPU at %s MHz\n",
- AT91_CPU_NAME,
+ CONFIG_SYS_AT91_CPU_NAME,
strmhz(temp, get_cpu_clk_rate()));
dram_size = 0;
nand_size += nand_info[i].size;
lcd_printf("\n%s\n", U_BOOT_VERSION);
- lcd_printf("%s CPU at %s MHz\n", AT91_CPU_NAME,
+ lcd_printf("%s CPU at %s MHz\n", CONFIG_SYS_AT91_CPU_NAME,
strmhz(temp, get_cpu_clk_rate()));
lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
dram_size >> 20,
lcd_printf ("(C) 2009 Ronetix GmbH\n");
lcd_printf ("support@ronetix.at\n");
lcd_printf ("%s CPU at %s MHz",
- AT91_CPU_NAME,
+ CONFIG_SYS_AT91_CPU_NAME,
strmhz(temp, get_cpu_clk_rate()));
dram_size = 0;
lcd_printf ("(C) 2009 Ronetix GmbH\n");
lcd_printf ("support@ronetix.at\n");
lcd_printf ("%s CPU at %s MHz",
- AT91_CPU_NAME,
+ CONFIG_SYS_AT91_CPU_NAME,
strmhz(temp, get_cpu_clk_rate()));
dram_size = 0;
{
unsigned freq, mckr;
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
-#ifndef AT91_MAIN_CLOCK
+#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
unsigned tmp;
/*
* When the bootloader initialized the main oscillator correctly,
#include <asm/arch/clk.h>
#include <asm/arch/io.h>
-#ifndef AT91_MAIN_CLOCK
-#define AT91_MAIN_CLOCK 0
+#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
+#define CONFIG_SYS_AT91_MAIN_CLOCK 0
#endif
int arch_cpu_init(void)
{
- return at91_clock_init(AT91_MAIN_CLOCK);
+ return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
}
#if defined(CONFIG_DISPLAY_CPUINFO)
{
char buf[32];
- printf("CPU: %s\n", AT91_CPU_NAME);
+ printf("CPU: %s\n", CONFIG_SYS_AT91_CPU_NAME);
printf("Crystal frequency: %8s MHz\n",
strmhz(buf, get_main_clk_rate()));
printf("CPU clock : %8s MHz\n",
/*
* Cpu Name
*/
-#define AT91_CPU_NAME "AT91CAP9"
+#define CONFIG_SYS_AT91_CPU_NAME "AT91CAP9"
#endif
#define AT91_PMX_CA_NCS7 0x00002000
#define AT91_PMX_CA_D16_31 0xFFFF0000
-#define AT91_CPU_NAME "AT91RM9200"
+#define CONFIG_SYS_AT91_CPU_NAME "AT91RM9200"
#endif
* Cpu Name
*/
#if defined(CONFIG_AT91SAM9260)
-#define AT91_CPU_NAME "AT91SAM9260"
+#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9260"
#elif defined(CONFIG_AT91SAM9G20)
-#define AT91_CPU_NAME "AT91SAM9G20"
+#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G20"
#endif
#endif
/*
* Cpu Name
*/
-#define AT91_CPU_NAME "AT91SAM9261"
+#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261"
#endif
/*
* Cpu Name
*/
-#define AT91_CPU_NAME "AT91SAM9263"
+#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263"
#endif
/*
* Cpu Name
*/
-#define AT91_CPU_NAME "AT91SAM9G45"
+#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G45"
#endif
/*
* Cpu Name
*/
-#define AT91_CPU_NAME "AT91SAM9RL"
+#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9RL"
#endif
#define CONFIG_AT91_LEGACY
/* ARM asynchronous clock */
-#define AT91_MAIN_CLOCK 18429952 /* from 18.432 MHz crystal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK 18429952 /* from 18.432 MHz crystal */
#define CONFIG_SYS_HZ 1000
#define CONFIG_AT91SAM9260 1 /* It's an Atmel AT91SAM9260 SoC*/
#define CONFIG_AT91_LEGACY
/* ARM asynchronous clock */
-#define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
#define CONFIG_SYS_HZ 1000
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
#define CONFIG_AT91_LEGACY
/* ARM asynchronous clock */
-#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
#define CONFIG_SYS_HZ 1000
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
#define CONFIG_AT91_LEGACY
/* ARM asynchronous clock */
-#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
#define CONFIG_SYS_HZ 1000
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
#define __CONFIG_H
/* ARM asynchronous clock */
-#define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
#define CONFIG_SYS_HZ 1000
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
#define CONFIG_AT91_LEGACY
/* ARM asynchronous clock */
-#define AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
#define CONFIG_SYS_HZ 1000
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
#define CONFIG_AT91_LEGACY
/* ARM asynchronous clock */
-#define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
#define CONFIG_SYS_HZ 1000
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
#define CONFIG_DISPLAY_CPUINFO 1
-#define AT91_MAIN_CLOCK 18432000
+#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
#define CONFIG_SYS_HZ 1000
#define CONFIG_ARM926EJS 1
#define CONFIG_AT91_LEGACY
/* ARM asynchronous clock */
-#define AT91_CPU_NAME "AT91SAM9261"
+#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261"
#define CONFIG_DISPLAY_BOARDINFO
#define MASTER_PLL_DIV 15
#define MASTER_PLL_MUL 162
#define MAIN_PLL_DIV 2
-#define AT91_MAIN_CLOCK 18432000
+#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
#define CONFIG_SYS_HZ 1000
#define MASTER_PLL_DIV 6
#define MASTER_PLL_MUL 65
#define MAIN_PLL_DIV 2 /* 2 or 4 */
-#define AT91_MAIN_CLOCK 18432000
+#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
#define CONFIG_SYS_HZ 1000
#endif
/* ARM asynchronous clock */
-#define AT91_MAIN_CLOCK 12000000 /* 12.000 MHz crystal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12.000 MHz crystal */
#define CONFIG_SYS_HZ 1000
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
#endif
/* ARM asynchronous clock */
-#define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
#define CONFIG_SYS_HZ 1000
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */