case RISCV::BI__builtin_riscv_clz_32:
case RISCV::BI__builtin_riscv_clz_64: {
Function *F = CGM.getIntrinsic(Intrinsic::ctlz, Ops[0]->getType());
- return Builder.CreateCall(F, {Ops[0], Builder.getInt1(false)});
+ Value *Result = Builder.CreateCall(F, {Ops[0], Builder.getInt1(false)});
+ if (Result->getType() != ResultType)
+ Result = Builder.CreateIntCast(Result, ResultType, /*isSigned*/true,
+ "cast");
+ return Result;
}
case RISCV::BI__builtin_riscv_ctz_32:
case RISCV::BI__builtin_riscv_ctz_64: {
Function *F = CGM.getIntrinsic(Intrinsic::cttz, Ops[0]->getType());
- return Builder.CreateCall(F, {Ops[0], Builder.getInt1(false)});
+ Value *Result = Builder.CreateCall(F, {Ops[0], Builder.getInt1(false)});
+ if (Result->getType() != ResultType)
+ Result = Builder.CreateIntCast(Result, ResultType, /*isSigned*/true,
+ "cast");
+ return Result;
}
// Zbc
// RV64XTHEADBB-LABEL: @clz_64(
// RV64XTHEADBB-NEXT: entry:
-// RV64XTHEADBB-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
// RV64XTHEADBB-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// RV64XTHEADBB-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
// RV64XTHEADBB-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
// RV64XTHEADBB-NEXT: [[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[TMP0]], i1 false)
-// RV64XTHEADBB-NEXT: store i64 [[TMP1]], ptr [[RETVAL]], align 4
-// RV64XTHEADBB-NEXT: [[TMP2:%.*]] = load i32, ptr [[RETVAL]], align 4
-// RV64XTHEADBB-NEXT: ret i32 [[TMP2]]
+// RV64XTHEADBB-NEXT: [[CAST:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64XTHEADBB-NEXT: ret i32 [[CAST]]
//
int clz_64(long a) {
return __builtin_riscv_clz_64(a);
// RV64XTHEADBB-LABEL: @clo_64(
// RV64XTHEADBB-NEXT: entry:
-// RV64XTHEADBB-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
// RV64XTHEADBB-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// RV64XTHEADBB-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
// RV64XTHEADBB-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
// RV64XTHEADBB-NEXT: [[NOT:%.*]] = xor i64 [[TMP0]], -1
// RV64XTHEADBB-NEXT: [[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[NOT]], i1 false)
-// RV64XTHEADBB-NEXT: store i64 [[TMP1]], ptr [[RETVAL]], align 4
-// RV64XTHEADBB-NEXT: [[TMP2:%.*]] = load i32, ptr [[RETVAL]], align 4
-// RV64XTHEADBB-NEXT: ret i32 [[TMP2]]
+// RV64XTHEADBB-NEXT: [[CAST:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64XTHEADBB-NEXT: ret i32 [[CAST]]
//
int clo_64(long a) {
return __builtin_riscv_clz_64(~a);
// RV64ZBB-LABEL: @clz_64(
// RV64ZBB-NEXT: entry:
-// RV64ZBB-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
// RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// RV64ZBB-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
// RV64ZBB-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
// RV64ZBB-NEXT: [[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[TMP0]], i1 false)
-// RV64ZBB-NEXT: store i64 [[TMP1]], ptr [[RETVAL]], align 4
-// RV64ZBB-NEXT: [[TMP2:%.*]] = load i32, ptr [[RETVAL]], align 4
-// RV64ZBB-NEXT: ret i32 [[TMP2]]
+// RV64ZBB-NEXT: [[CAST:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64ZBB-NEXT: ret i32 [[CAST]]
//
int clz_64(unsigned long a) {
return __builtin_riscv_clz_64(a);
// RV64ZBB-LABEL: @ctz_64(
// RV64ZBB-NEXT: entry:
-// RV64ZBB-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
// RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// RV64ZBB-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
// RV64ZBB-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
// RV64ZBB-NEXT: [[TMP1:%.*]] = call i64 @llvm.cttz.i64(i64 [[TMP0]], i1 false)
-// RV64ZBB-NEXT: store i64 [[TMP1]], ptr [[RETVAL]], align 4
-// RV64ZBB-NEXT: [[TMP2:%.*]] = load i32, ptr [[RETVAL]], align 4
-// RV64ZBB-NEXT: ret i32 [[TMP2]]
+// RV64ZBB-NEXT: [[CAST:%.*]] = trunc i64 [[TMP1]] to i32
+// RV64ZBB-NEXT: ret i32 [[CAST]]
//
int ctz_64(unsigned long a) {
return __builtin_riscv_ctz_64(a);