-;; Machine description for SPARC chip for GCC
-;; Copyright (C) 1987-2016 Free Software Foundation, Inc.
-;; Contributed by Michael Tiemann (tiemann@cygnus.com)
-;; 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
-;; at Cygnus Support.
+;; Machine description for SPARC.
+;; Copyright (C) 1987-2016 Free Software Foundation, Inc.
+;; Contributed by Michael Tiemann (tiemann@cygnus.com)
+;; 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
+;; at Cygnus Support.
;; This file is part of GCC.
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
-;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-
(define_c_enum "unspec" [
UNSPEC_MOVE_PIC
UNSPEC_UPDATE_RETURN
(GSR_REG 102)
])
-(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
(define_mode_iterator I [QI HI SI DI])
+(define_mode_iterator P [(SI "TARGET_ARCH32") (DI "TARGET_ARCH64")])
(define_mode_iterator W [SI (DI "TARGET_ARCH64")])
(define_mode_iterator F [SF DF TF])
(const_int 0)))]
"TARGET_ARCH64 && !TARGET_VIS3"
"#"
- "&& ! reg_overlap_mentioned_p (operands[1], operands[0])"
+ "&& !reg_overlap_mentioned_p (operands[1], operands[0])"
[(set (match_dup 0) (const_int 0))
(set (match_dup 0) (if_then_else:W (ne:DI (match_dup 1) (const_int 0))
(const_int 1)
(const_int 0))))]
"TARGET_ARCH64 && !TARGET_SUBXC"
"#"
- "&& ! reg_overlap_mentioned_p (operands[1], operands[0])"
+ "&& !reg_overlap_mentioned_p (operands[1], operands[0])"
[(set (match_dup 0) (const_int 0))
(set (match_dup 0) (if_then_else:W (ne:DI (match_dup 1) (const_int 0))
(const_int -1)
(const_int 0)))]
"TARGET_ARCH64"
"#"
- "&& ! reg_overlap_mentioned_p (operands[1], operands[0])"
+ "&& !reg_overlap_mentioned_p (operands[1], operands[0])"
[(set (match_dup 0) (const_int 0))
(set (match_dup 0) (if_then_else:W (eq:DI (match_dup 1) (const_int 0))
(const_int 1)
(const_int 0))))]
"TARGET_ARCH64"
"#"
- "&& ! reg_overlap_mentioned_p (operands[1], operands[0])"
+ "&& !reg_overlap_mentioned_p (operands[1], operands[0])"
[(set (match_dup 0) (const_int 0))
(set (match_dup 0) (if_then_else:W (eq:DI (match_dup 1) (const_int 0))
(const_int -1)
(define_split
[(set (match_operand:W 0 "register_operand" "")
(match_operator:W 1 "icc_comparison_operator"
- [(match_operand 2 "icc_register_operand" "") (const_int 0)]))]
+ [(match_operand 2 "icc_register_operand" "") (const_int 0)]))]
"TARGET_V9
/* 64-bit LTU is better implemented using addxc with VIS3. */
&& !(GET_CODE (operands[1]) == LTU
(define_expand "cbranchcc4"
[(set (pc)
(if_then_else (match_operator 0 "comparison_operator"
- [(match_operand 1 "compare_operand" "")
- (match_operand 2 "const_zero_operand" "")])
+ [(match_operand 1 "compare_operand" "")
+ (match_operand 2 "const_zero_operand" "")])
(label_ref (match_operand 3 "" ""))
(pc)))]
""
(match_operand:F 2 "register_operand" "")]))
(use (match_operand 3 ""))]
"TARGET_FPU"
- { emit_conditional_branch_insn (operands); DONE; })
+{
+ emit_conditional_branch_insn (operands);
+ DONE;
+})
;; Now match both normal and inverted jump.
(define_insn "*normal_branch"
[(set (pc)
(if_then_else (match_operator 0 "icc_comparison_operator"
- [(reg CC_REG) (const_int 0)])
+ [(reg CC_REG) (const_int 0)])
(label_ref (match_operand 1 "" ""))
(pc)))]
""
(define_insn "*inverted_branch"
[(set (pc)
(if_then_else (match_operator 0 "icc_comparison_operator"
- [(reg CC_REG) (const_int 0)])
+ [(reg CC_REG) (const_int 0)])
(pc)
(label_ref (match_operand 1 "" ""))))]
""
(define_insn "*normal_fp_branch"
[(set (pc)
(if_then_else (match_operator 1 "comparison_operator"
- [(match_operand:CCFP 0 "fcc_register_operand" "c")
- (const_int 0)])
+ [(match_operand:CCFP 0 "fcc_register_operand" "c")
+ (const_int 0)])
(label_ref (match_operand 2 "" ""))
(pc)))]
""
(define_insn "*inverted_fp_branch"
[(set (pc)
(if_then_else (match_operator 1 "comparison_operator"
- [(match_operand:CCFP 0 "fcc_register_operand" "c")
- (const_int 0)])
+ [(match_operand:CCFP 0 "fcc_register_operand" "c")
+ (const_int 0)])
(pc)
(label_ref (match_operand 2 "" ""))))]
""
(define_insn "*normal_fpe_branch"
[(set (pc)
(if_then_else (match_operator 1 "comparison_operator"
- [(match_operand:CCFPE 0 "fcc_register_operand" "c")
- (const_int 0)])
+ [(match_operand:CCFPE 0 "fcc_register_operand" "c")
+ (const_int 0)])
(label_ref (match_operand 2 "" ""))
(pc)))]
""
(define_insn "*inverted_fpe_branch"
[(set (pc)
(if_then_else (match_operator 1 "comparison_operator"
- [(match_operand:CCFPE 0 "fcc_register_operand" "c")
- (const_int 0)])
+ [(match_operand:CCFPE 0 "fcc_register_operand" "c")
+ (const_int 0)])
(pc)
(label_ref (match_operand 2 "" ""))))]
""
(define_insn "*normal_int_branch_sp64"
[(set (pc)
(if_then_else (match_operator 0 "v9_register_comparison_operator"
- [(match_operand:DI 1 "register_operand" "r")
- (const_int 0)])
+ [(match_operand:DI 1 "register_operand" "r")
+ (const_int 0)])
(label_ref (match_operand 2 "" ""))
(pc)))]
"TARGET_ARCH64"
(define_insn "*inverted_int_branch_sp64"
[(set (pc)
(if_then_else (match_operator 0 "v9_register_comparison_operator"
- [(match_operand:DI 1 "register_operand" "r")
- (const_int 0)])
+ [(match_operand:DI 1 "register_operand" "r")
+ (const_int 0)])
(pc)
(label_ref (match_operand 2 "" ""))))]
"TARGET_ARCH64"
[(set (match_operand:P 0 "register_operand" "=r")
(unspec:P [(match_operand:P 1 "symbolic_operand" "")
(match_operand:P 2 "call_address_operand" "")
- (match_operand:P 3 "const_int_operand" "")] UNSPEC_LOAD_PCREL_SYM))
+ (match_operand:P 3 "const_int_operand" "")]
+ UNSPEC_LOAD_PCREL_SYM))
(clobber (reg:P O7_REG))]
"REGNO (operands[0]) == INTVAL (operands[3])"
{
(define_insn "movsi_lo_sum_pic"
[(set (match_operand:SI 0 "register_operand" "=r")
(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
- (unspec:SI [(match_operand:SI 2 "immediate_operand" "in")] UNSPEC_MOVE_PIC)))]
+ (unspec:SI [(match_operand:SI 2 "immediate_operand" "in")]
+ UNSPEC_MOVE_PIC)))]
"flag_pic"
{
#ifdef HAVE_AS_SPARC_GOTDATA_OP
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "register_operand" "r")
- (match_operand 3 "symbolic_operand" "")] UNSPEC_MOVE_GOTDATA))]
+ (match_operand 3 "symbolic_operand" "")]
+ UNSPEC_MOVE_GOTDATA))]
"flag_pic && check_pic (1)"
{
#ifdef HAVE_AS_SPARC_GOTDATA_OP
(define_insn "*movdi_insn_sp32"
[(set (match_operand:DI 0 "nonimmediate_operand"
- "=T,o,T,U,o,r,r,r,?T,?*f,?*f,?o,?*e,?*e, r,?*f,?*e,?W,b,b")
+ "=T,o,T,U,o,r,r,r,?T,?*f,?*f,?o,?*e,?*e, r,?*f,?*e,?W,b,b")
(match_operand:DI 1 "input_operand"
- " J,J,U,T,r,o,i,r,*f, T, o,*f, *e, *e,?*f, r, W,*e,J,P"))]
- "! TARGET_ARCH64
+ " J,J,U,T,r,o,i,r,*f, T, o,*f, *e, *e,?*f, r, W,*e,J,P"))]
+ "TARGET_ARCH32
&& (register_operand (operands[0], DImode)
|| register_or_zero_operand (operands[1], DImode))"
"@
(define_insn "movdi_lo_sum_pic"
[(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
- (unspec:DI [(match_operand:DI 2 "immediate_operand" "in")] UNSPEC_MOVE_PIC)))]
+ (unspec:DI [(match_operand:DI 2 "immediate_operand" "in")]
+ UNSPEC_MOVE_PIC)))]
"TARGET_ARCH64 && flag_pic"
{
#ifdef HAVE_AS_SPARC_GOTDATA_OP
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "register_operand" "r")
- (match_operand 3 "symbolic_operand" "")] UNSPEC_MOVE_GOTDATA))]
+ (match_operand 3 "symbolic_operand" "")]
+ UNSPEC_MOVE_GOTDATA))]
"TARGET_ARCH64 && flag_pic && check_pic (1)"
{
#ifdef HAVE_AS_SPARC_GOTDATA_OP
(define_insn "seth44"
[(set (match_operand:DI 0 "register_operand" "=r")
- (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETH44)))]
+ (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
+ UNSPEC_SETH44)))]
"TARGET_CM_MEDMID"
"sethi\t%%h44(%a1), %0")
(define_insn "setm44"
[(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
- (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] UNSPEC_SETM44)))]
+ (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
+ UNSPEC_SETM44)))]
"TARGET_CM_MEDMID"
"or\t%1, %%m44(%a2), %0")
(define_insn "sethh"
[(set (match_operand:DI 0 "register_operand" "=r")
- (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETHH)))]
+ (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
+ UNSPEC_SETHH)))]
"TARGET_CM_MEDANY"
"sethi\t%%hh(%a1), %0")
(define_insn "setlm"
[(set (match_operand:DI 0 "register_operand" "=r")
- (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETLM)))]
+ (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
+ UNSPEC_SETLM)))]
"TARGET_CM_MEDANY"
"sethi\t%%lm(%a1), %0")
(define_insn "sethm"
[(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
- (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] UNSPEC_EMB_SETHM)))]
+ (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
+ UNSPEC_EMB_SETHM)))]
"TARGET_CM_MEDANY"
"or\t%1, %%hm(%a2), %0")
(define_insn "embmedany_sethi"
[(set (match_operand:DI 0 "register_operand" "=r")
- (high:DI (unspec:DI [(match_operand:DI 1 "data_segment_operand" "")] UNSPEC_EMB_HISUM)))]
+ (high:DI (unspec:DI [(match_operand:DI 1 "data_segment_operand" "")]
+ UNSPEC_EMB_HISUM)))]
"TARGET_CM_EMBMEDANY && check_pic (1)"
"sethi\t%%hi(%a1), %0")
(define_insn "embmedany_brsum"
[(set (match_operand:DI 0 "register_operand" "=r")
- (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_EMB_HISUM))]
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+ UNSPEC_EMB_HISUM))]
"TARGET_CM_EMBMEDANY"
"add\t%1, %_, %0")
(define_insn "embmedany_textuhi"
[(set (match_operand:DI 0 "register_operand" "=r")
- (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] UNSPEC_EMB_TEXTUHI)))]
+ (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")]
+ UNSPEC_EMB_TEXTUHI)))]
"TARGET_CM_EMBMEDANY && check_pic (1)"
"sethi\t%%uhi(%a1), %0")
(define_insn "embmedany_texthi"
[(set (match_operand:DI 0 "register_operand" "=r")
- (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] UNSPEC_EMB_TEXTHI)))]
+ (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")]
+ UNSPEC_EMB_TEXTHI)))]
"TARGET_CM_EMBMEDANY && check_pic (1)"
"sethi\t%%hi(%a1), %0")
(define_insn "embmedany_textulo"
[(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
- (unspec:DI [(match_operand:DI 2 "text_segment_operand" "")] UNSPEC_EMB_TEXTULO)))]
+ (unspec:DI [(match_operand:DI 2 "text_segment_operand" "")]
+ UNSPEC_EMB_TEXTULO)))]
"TARGET_CM_EMBMEDANY"
"or\t%1, %%ulo(%a2), %0")
(match_operand:TI 2 "register_operand" "=&r")])]
"(TARGET_CM_MEDANY
|| TARGET_CM_EMBMEDANY)
- && ! flag_pic"
+ && !flag_pic"
{
sparc_emit_set_symbolic_const64 (operands[0], operands[1], operands[2]);
DONE;
(match_operand:TI 2 "register_operand" "=&r")])]
"(TARGET_CM_MEDANY
|| TARGET_CM_EMBMEDANY)
- && ! flag_pic"
+ && !flag_pic"
{
sparc_emit_set_symbolic_const64 (operands[0], operands[1], operands[2]);
DONE;
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "const_int_operand" ""))]
- "! TARGET_ARCH64
+ "TARGET_ARCH32
&& ((GET_CODE (operands[0]) == REG
&& SPARC_INT_REG_P (REGNO (operands[0])))
|| (GET_CODE (operands[0]) == SUBREG
/* Slick... but this trick loses if this subreg constant part
can be done in one insn. */
if (low == high
- && ! SPARC_SETHI32_P (high)
- && ! SPARC_SIMM13_P (high))
+ && !SPARC_SETHI32_P (high)
+ && !SPARC_SIMM13_P (high))
emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
gen_highpart (SImode, operands[0])));
else
[(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "register_operand" ""))]
"reload_completed
- && (! TARGET_V9
- || (! TARGET_ARCH64
- && sparc_split_regreg_legitimate (operands[0],
- operands[1])))"
+ && (!TARGET_V9
+ || (TARGET_ARCH32
+ && sparc_split_regreg_legitimate (operands[0], operands[1])))"
[(clobber (const_int 0))]
{
rtx set_dest = operands[0];
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "memory_operand" ""))]
- "(! TARGET_ARCH64
+ "(TARGET_ARCH32
&& reload_completed
&& sparc_splitdi_legitimate (operands[0], operands[1]))"
[(clobber (const_int 0))]
(define_split
[(set (match_operand:DI 0 "memory_operand" "")
(match_operand:DI 1 "register_operand" ""))]
- "(! TARGET_ARCH64
+ "(TARGET_ARCH32
&& reload_completed
&& sparc_splitdi_legitimate (operands[1], operands[0]))"
[(clobber (const_int 0))]
[(set (match_operand:DI 0 "memory_operand" "")
(match_operand:DI 1 "const_zero_operand" ""))]
"reload_completed
- && (! TARGET_V9
- || (! TARGET_ARCH64
- && ! mem_min_alignment (operands[0], 8)))
+ && (!TARGET_V9
+ || (TARGET_ARCH32
+ && !mem_min_alignment (operands[0], 8)))
&& offsettable_memref_p (operands[0])"
[(clobber (const_int 0))]
{
[(set (match_operand:TI 0 "nonimmediate_operand" "=r , o,?*e,?o,b")
(match_operand:TI 1 "input_operand" "roJ,rJ, eo, e,J"))]
"TARGET_ARCH64
- && ! TARGET_HARD_QUAD
+ && !TARGET_HARD_QUAD
&& (register_operand (operands[0], TImode)
|| register_or_zero_operand (operands[1], TImode))"
"#"
(match_operand:TI 1 "register_operand" ""))]
"reload_completed
&& ((TARGET_FPU
- && ! TARGET_HARD_QUAD)
- || (! fp_register_operand (operands[0], TImode)
- && ! fp_register_operand (operands[1], TImode)))"
+ && !TARGET_HARD_QUAD)
+ || (!fp_register_operand (operands[0], TImode)
+ && !fp_register_operand (operands[1], TImode)))"
[(clobber (const_int 0))]
{
rtx set_dest = operands[0];
(match_operand:TI 1 "memory_operand" ""))]
"reload_completed
&& offsettable_memref_p (operands[1])
- && (! TARGET_HARD_QUAD
- || ! fp_register_operand (operands[0], TImode))"
+ && (!TARGET_HARD_QUAD
+ || !fp_register_operand (operands[0], TImode))"
[(clobber (const_int 0))]
{
rtx word0 = adjust_address (operands[1], DImode, 0);
(match_operand:TI 1 "register_operand" ""))]
"reload_completed
&& offsettable_memref_p (operands[0])
- && (! TARGET_HARD_QUAD
- || ! fp_register_operand (operands[1], TImode))"
+ && (!TARGET_HARD_QUAD
+ || !fp_register_operand (operands[1], TImode))"
[(clobber (const_int 0))]
{
rtx set_src = operands[1];
})
(define_insn "*movdf_insn_sp32"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=b,b,e,e,*r, f, e,T,W,U,T, f, *r, o,o")
- (match_operand:DF 1 "input_operand" "G,C,e,e, f,*r,W#F,G,e,T,U,o#F,*roF,*rG,f"))]
- "! TARGET_ARCH64
+ [(set (match_operand:DF 0 "nonimmediate_operand"
+ "=b,b,e,e,*r, f, e,T,W,U,T, f, *r, o,o")
+ (match_operand:DF 1 "input_operand"
+ " G,C,e,e, f,*r,W#F,G,e,T,U,o#F,*roF,*rG,f"))]
+ "TARGET_ARCH32
&& (register_operand (operands[0], DFmode)
|| register_or_zero_or_all_ones_operand (operands[1], DFmode))"
"@
(match_operand:DF 1 "const_double_operand" ""))]
"REG_P (operands[0])
&& SPARC_INT_REG_P (REGNO (operands[0]))
- && ! const_zero_operand (operands[1], GET_MODE (operands[0]))
+ && !const_zero_operand (operands[1], GET_MODE (operands[0]))
&& reload_completed"
[(clobber (const_int 0))]
{
/* Slick... but this trick loses if this subreg constant part
can be done in one insn. */
if (lo == hi
- && ! SPARC_SETHI32_P (INTVAL (hi))
- && ! SPARC_SIMM13_P (INTVAL (hi)))
+ && !SPARC_SETHI32_P (INTVAL (hi))
+ && !SPARC_SIMM13_P (INTVAL (hi)))
{
emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
gen_highpart (SImode, operands[0])));
(define_split
[(set (match_operand:DF 0 "register_operand" "")
(match_operand:DF 1 "register_operand" ""))]
- "(! TARGET_V9
- || (! TARGET_ARCH64
- && sparc_split_regreg_legitimate (operands[0],
- operands[1])))
+ "(!TARGET_V9
+ || (TARGET_ARCH32
+ && sparc_split_regreg_legitimate (operands[0], operands[1])))
&& reload_completed"
[(clobber (const_int 0))]
{
[(set (match_operand:DF 0 "register_operand" "")
(match_operand:DF 1 "memory_operand" ""))]
"reload_completed
- && ! TARGET_ARCH64
+ && TARGET_ARCH32
&& (((REGNO (operands[0]) % 2) != 0)
- || ! mem_min_alignment (operands[1], 8))
+ || !mem_min_alignment (operands[1], 8))
&& offsettable_memref_p (operands[1])"
[(clobber (const_int 0))]
{
[(set (match_operand:DF 0 "memory_operand" "")
(match_operand:DF 1 "register_operand" ""))]
"reload_completed
- && ! TARGET_ARCH64
+ && TARGET_ARCH32
&& (((REGNO (operands[1]) % 2) != 0)
- || ! mem_min_alignment (operands[0], 8))
+ || !mem_min_alignment (operands[0], 8))
&& offsettable_memref_p (operands[0])"
[(clobber (const_int 0))]
{
[(set (match_operand:DF 0 "memory_operand" "")
(match_operand:DF 1 "const_zero_operand" ""))]
"reload_completed
- && (! TARGET_V9
- || (! TARGET_ARCH64
- && ! mem_min_alignment (operands[0], 8)))
+ && (!TARGET_V9
+ || (TARGET_ARCH32
+ && !mem_min_alignment (operands[0], 8)))
&& offsettable_memref_p (operands[0])"
[(clobber (const_int 0))]
{
[(set (match_operand:DF 0 "register_operand" "")
(match_operand:DF 1 "const_zero_operand" ""))]
"reload_completed
- && ! TARGET_ARCH64
+ && TARGET_ARCH32
&& ((GET_CODE (operands[0]) == REG
&& SPARC_INT_REG_P (REGNO (operands[0])))
|| (GET_CODE (operands[0]) == SUBREG
(define_insn "*movtf_insn_sp32"
[(set (match_operand:TF 0 "nonimmediate_operand" "=b, e,o, o,U, r")
(match_operand:TF 1 "input_operand" " G,oe,e,rGU,o,roG"))]
- "! TARGET_ARCH64
+ "TARGET_ARCH32
&& (register_operand (operands[0], TFmode)
|| register_or_zero_operand (operands[1], TFmode))"
"#"
[(set (match_operand:TF 0 "nonimmediate_operand" "=b, e,o, o, r")
(match_operand:TF 1 "input_operand" "G,oe,e,rG,roG"))]
"TARGET_ARCH64
- && ! TARGET_HARD_QUAD
+ && !TARGET_HARD_QUAD
&& (register_operand (operands[0], TFmode)
|| register_or_zero_operand (operands[1], TFmode))"
"#"
[(set (match_operand:TF 0 "register_operand" "")
(match_operand:TF 1 "register_operand" ""))]
"reload_completed
- && (! TARGET_ARCH64
+ && (TARGET_ARCH32
|| (TARGET_FPU
- && ! TARGET_HARD_QUAD)
- || (! fp_register_operand (operands[0], TFmode)
- && ! fp_register_operand (operands[1], TFmode)))"
+ && !TARGET_HARD_QUAD)
+ || (!fp_register_operand (operands[0], TFmode)
+ && !fp_register_operand (operands[1], TFmode)))"
[(clobber (const_int 0))]
{
rtx set_dest = operands[0];
(match_operand:TF 1 "memory_operand" ""))]
"(reload_completed
&& offsettable_memref_p (operands[1])
- && (! TARGET_ARCH64
- || ! TARGET_HARD_QUAD
- || ! fp_register_operand (operands[0], TFmode)))"
+ && (TARGET_ARCH32
+ || !TARGET_HARD_QUAD
+ || !fp_register_operand (operands[0], TFmode)))"
[(clobber (const_int 0))]
{
rtx word0 = adjust_address (operands[1], DFmode, 0);
(match_operand:TF 1 "register_operand" ""))]
"(reload_completed
&& offsettable_memref_p (operands[0])
- && (! TARGET_ARCH64
- || ! TARGET_HARD_QUAD
- || ! fp_register_operand (operands[1], TFmode)))"
+ && (TARGET_ARCH32
+ || !TARGET_HARD_QUAD
+ || !fp_register_operand (operands[1], TFmode)))"
[(clobber (const_int 0))]
{
rtx set_src = operands[1];
(match_operand:I 3 "arith10_operand" "")))]
"TARGET_V9 && !(<I:MODE>mode == DImode && TARGET_ARCH32)"
{
- if (! sparc_expand_conditional_move (<I:MODE>mode, operands))
+ if (!sparc_expand_conditional_move (<I:MODE>mode, operands))
FAIL;
DONE;
})
(match_operand:F 3 "register_operand" "")))]
"TARGET_V9 && TARGET_FPU"
{
- if (! sparc_expand_conditional_move (<F:MODE>mode, operands))
+ if (!sparc_expand_conditional_move (<F:MODE>mode, operands))
FAIL;
DONE;
})
(define_insn "*mov<I:mode>_cc_v9"
[(set (match_operand:I 0 "register_operand" "=r")
(if_then_else:I (match_operator 1 "icc_or_fcc_comparison_operator"
- [(match_operand 2 "icc_or_fcc_register_operand" "X")
- (const_int 0)])
+ [(match_operand 2 "icc_or_fcc_register_operand" "X")
+ (const_int 0)])
(match_operand:I 3 "arith11_operand" "rL")
(match_operand:I 4 "register_operand" "0")))]
"TARGET_V9 && !(<I:MODE>mode == DImode && TARGET_ARCH32)"
(define_insn "*mov<I:mode>_cc_reg_sp64"
[(set (match_operand:I 0 "register_operand" "=r")
(if_then_else:I (match_operator 1 "v9_register_comparison_operator"
- [(match_operand:DI 2 "register_operand" "r")
- (const_int 0)])
+ [(match_operand:DI 2 "register_operand" "r")
+ (const_int 0)])
(match_operand:I 3 "arith10_operand" "rM")
(match_operand:I 4 "register_operand" "0")))]
"TARGET_ARCH64"
(define_insn "*movsf_cc_v9"
[(set (match_operand:SF 0 "register_operand" "=f")
(if_then_else:SF (match_operator 1 "icc_or_fcc_comparison_operator"
- [(match_operand 2 "icc_or_fcc_register_operand" "X")
- (const_int 0)])
+ [(match_operand 2 "icc_or_fcc_register_operand" "X")
+ (const_int 0)])
(match_operand:SF 3 "register_operand" "f")
(match_operand:SF 4 "register_operand" "0")))]
"TARGET_V9 && TARGET_FPU"
(define_insn "*movsf_cc_reg_sp64"
[(set (match_operand:SF 0 "register_operand" "=f")
(if_then_else:SF (match_operator 1 "v9_register_comparison_operator"
- [(match_operand:DI 2 "register_operand" "r")
- (const_int 0)])
+ [(match_operand:DI 2 "register_operand" "r")
+ (const_int 0)])
(match_operand:SF 3 "register_operand" "f")
(match_operand:SF 4 "register_operand" "0")))]
"TARGET_ARCH64 && TARGET_FPU"
(define_insn "movdf_cc_v9"
[(set (match_operand:DF 0 "register_operand" "=e")
(if_then_else:DF (match_operator 1 "icc_or_fcc_comparison_operator"
- [(match_operand 2 "icc_or_fcc_register_operand" "X")
- (const_int 0)])
+ [(match_operand 2 "icc_or_fcc_register_operand" "X")
+ (const_int 0)])
(match_operand:DF 3 "register_operand" "e")
(match_operand:DF 4 "register_operand" "0")))]
"TARGET_V9 && TARGET_FPU"
(define_insn "movdf_cc_reg_sp64"
[(set (match_operand:DF 0 "register_operand" "=e")
(if_then_else:DF (match_operator 1 "v9_register_comparison_operator"
- [(match_operand:DI 2 "register_operand" "r")
- (const_int 0)])
+ [(match_operand:DI 2 "register_operand" "r")
+ (const_int 0)])
(match_operand:DF 3 "register_operand" "e")
(match_operand:DF 4 "register_operand" "0")))]
"TARGET_ARCH64 && TARGET_FPU"
(define_insn "*movtf_cc_hq_v9"
[(set (match_operand:TF 0 "register_operand" "=e")
(if_then_else:TF (match_operator 1 "icc_or_fcc_comparison_operator"
- [(match_operand 2 "icc_or_fcc_register_operand" "X")
- (const_int 0)])
+ [(match_operand 2 "icc_or_fcc_register_operand" "X")
+ (const_int 0)])
(match_operand:TF 3 "register_operand" "e")
(match_operand:TF 4 "register_operand" "0")))]
"TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD"
(define_insn "*movtf_cc_reg_hq_sp64"
[(set (match_operand:TF 0 "register_operand" "=e")
(if_then_else:TF (match_operator 1 "v9_register_comparison_operator"
- [(match_operand:DI 2 "register_operand" "r")
- (const_int 0)])
+ [(match_operand:DI 2 "register_operand" "r")
+ (const_int 0)])
(match_operand:TF 3 "register_operand" "e")
(match_operand:TF 4 "register_operand" "0")))]
"TARGET_ARCH64 && TARGET_FPU && TARGET_HARD_QUAD"
(define_insn_and_split "*movtf_cc_v9"
[(set (match_operand:TF 0 "register_operand" "=e")
(if_then_else:TF (match_operator 1 "icc_or_fcc_comparison_operator"
- [(match_operand 2 "icc_or_fcc_register_operand" "X")
- (const_int 0)])
+ [(match_operand 2 "icc_or_fcc_register_operand" "X")
+ (const_int 0)])
(match_operand:TF 3 "register_operand" "e")
(match_operand:TF 4 "register_operand" "0")))]
"TARGET_V9 && TARGET_FPU && !TARGET_HARD_QUAD"
if (reg_overlap_mentioned_p (dest1, srca2))
{
- emit_insn (gen_movdf_cc_v9 (dest2, operands[1], operands[2], srca2, dest2));
- emit_insn (gen_movdf_cc_v9 (dest1, operands[1], operands[2], srca1, dest1));
+ emit_insn (gen_movdf_cc_v9 (dest2, operands[1], operands[2],
+ srca2, dest2));
+ emit_insn (gen_movdf_cc_v9 (dest1, operands[1], operands[2],
+ srca1, dest1));
}
else
{
- emit_insn (gen_movdf_cc_v9 (dest1, operands[1], operands[2], srca1, dest1));
- emit_insn (gen_movdf_cc_v9 (dest2, operands[1], operands[2], srca2, dest2));
+ emit_insn (gen_movdf_cc_v9 (dest1, operands[1], operands[2],
+ srca1, dest1));
+ emit_insn (gen_movdf_cc_v9 (dest2, operands[1], operands[2],
+ srca2, dest2));
}
DONE;
}
(define_insn_and_split "*movtf_cc_reg_sp64"
[(set (match_operand:TF 0 "register_operand" "=e")
(if_then_else:TF (match_operator 1 "v9_register_comparison_operator"
- [(match_operand:DI 2 "register_operand" "r")
- (const_int 0)])
+ [(match_operand:DI 2 "register_operand" "r")
+ (const_int 0)])
(match_operand:TF 3 "register_operand" "e")
(match_operand:TF 4 "register_operand" "0")))]
- "TARGET_ARCH64 && TARGET_FPU && ! TARGET_HARD_QUAD"
+ "TARGET_ARCH64 && TARGET_FPU && !TARGET_HARD_QUAD"
"#"
"&& reload_completed"
[(clobber (const_int 0))]
if (reg_overlap_mentioned_p (dest1, srca2))
{
- emit_insn (gen_movdf_cc_reg_sp64 (dest2, operands[1], operands[2], srca2, dest2));
- emit_insn (gen_movdf_cc_reg_sp64 (dest1, operands[1], operands[2], srca1, dest1));
+ emit_insn (gen_movdf_cc_reg_sp64 (dest2, operands[1], operands[2],
+ srca2, dest2));
+ emit_insn (gen_movdf_cc_reg_sp64 (dest1, operands[1], operands[2],
+ srca1, dest1));
}
else
{
- emit_insn (gen_movdf_cc_reg_sp64 (dest1, operands[1], operands[2], srca1, dest1));
- emit_insn (gen_movdf_cc_reg_sp64 (dest2, operands[1], operands[2], srca2, dest2));
+ emit_insn (gen_movdf_cc_reg_sp64 (dest1, operands[1], operands[2],
+ srca1, dest1));
+ emit_insn (gen_movdf_cc_reg_sp64 (dest2, operands[1], operands[2],
+ srca2, dest2));
}
DONE;
}
(define_insn_and_split "*zero_extendsidi2_insn_sp32"
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
- "! TARGET_ARCH64"
+ "TARGET_ARCH32"
"#"
"&& reload_completed"
[(set (match_dup 2) (match_dup 1))
(define_insn "extendsfdf2"
[(set (match_operand:DF 0 "register_operand" "=e")
- (float_extend:DF
- (match_operand:SF 1 "register_operand" "f")))]
+ (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
"TARGET_FPU"
"fstod\t%1, %0"
[(set_attr "type" "fp")
(define_expand "extendsftf2"
[(set (match_operand:TF 0 "nonimmediate_operand" "")
- (float_extend:TF
- (match_operand:SF 1 "register_operand" "")))]
+ (float_extend:TF (match_operand:SF 1 "register_operand" "")))]
"TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
"emit_tfmode_cvt (FLOAT_EXTEND, operands); DONE;")
(define_insn "*extendsftf2_hq"
[(set (match_operand:TF 0 "register_operand" "=e")
- (float_extend:TF
- (match_operand:SF 1 "register_operand" "f")))]
+ (float_extend:TF (match_operand:SF 1 "register_operand" "f")))]
"TARGET_FPU && TARGET_HARD_QUAD"
"fstoq\t%1, %0"
[(set_attr "type" "fp")])
(define_expand "extenddftf2"
[(set (match_operand:TF 0 "nonimmediate_operand" "")
- (float_extend:TF
- (match_operand:DF 1 "register_operand" "")))]
+ (float_extend:TF (match_operand:DF 1 "register_operand" "")))]
"TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
"emit_tfmode_cvt (FLOAT_EXTEND, operands); DONE;")
(define_insn "*extenddftf2_hq"
[(set (match_operand:TF 0 "register_operand" "=e")
- (float_extend:TF
- (match_operand:DF 1 "register_operand" "e")))]
+ (float_extend:TF (match_operand:DF 1 "register_operand" "e")))]
"TARGET_FPU && TARGET_HARD_QUAD"
"fdtoq\t%1, %0"
[(set_attr "type" "fp")])
(define_insn "truncdfsf2"
[(set (match_operand:SF 0 "register_operand" "=f")
- (float_truncate:SF
- (match_operand:DF 1 "register_operand" "e")))]
+ (float_truncate:SF (match_operand:DF 1 "register_operand" "e")))]
"TARGET_FPU"
"fdtos\t%1, %0"
[(set_attr "type" "fp")
(define_expand "trunctfsf2"
[(set (match_operand:SF 0 "register_operand" "")
- (float_truncate:SF
- (match_operand:TF 1 "general_operand" "")))]
+ (float_truncate:SF (match_operand:TF 1 "general_operand" "")))]
"TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
"emit_tfmode_cvt (FLOAT_TRUNCATE, operands); DONE;")
(define_insn "*trunctfsf2_hq"
[(set (match_operand:SF 0 "register_operand" "=f")
- (float_truncate:SF
- (match_operand:TF 1 "register_operand" "e")))]
+ (float_truncate:SF (match_operand:TF 1 "register_operand" "e")))]
"TARGET_FPU && TARGET_HARD_QUAD"
"fqtos\t%1, %0"
[(set_attr "type" "fp")])
(define_expand "trunctfdf2"
[(set (match_operand:DF 0 "register_operand" "")
- (float_truncate:DF
- (match_operand:TF 1 "general_operand" "")))]
+ (float_truncate:DF (match_operand:TF 1 "general_operand" "")))]
"TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
"emit_tfmode_cvt (FLOAT_TRUNCATE, operands); DONE;")
(define_insn "*trunctfdf2_hq"
[(set (match_operand:DF 0 "register_operand" "=e")
- (float_truncate:DF
- (match_operand:TF 1 "register_operand" "e")))]
+ (float_truncate:DF (match_operand:TF 1 "register_operand" "e")))]
"TARGET_FPU && TARGET_HARD_QUAD"
"fqtod\t%1, %0"
[(set_attr "type" "fp")])
(define_expand "floatunssitf2"
[(set (match_operand:TF 0 "nonimmediate_operand" "")
(unsigned_float:TF (match_operand:SI 1 "register_operand" "")))]
- "TARGET_FPU && TARGET_ARCH64 && ! TARGET_HARD_QUAD"
+ "TARGET_FPU && TARGET_ARCH64 && !TARGET_HARD_QUAD"
"emit_tfmode_cvt (UNSIGNED_FLOAT, operands); DONE;")
;; Now the same for 64 bit sources.
(define_expand "floatunsditf2"
[(set (match_operand:TF 0 "nonimmediate_operand" "")
(unsigned_float:TF (match_operand:DI 1 "register_operand" "")))]
- "TARGET_FPU && TARGET_ARCH64 && ! TARGET_HARD_QUAD"
+ "TARGET_FPU && TARGET_ARCH64 && !TARGET_HARD_QUAD"
"emit_tfmode_cvt (UNSIGNED_FLOAT, operands); DONE;")
;; Convert a float to an actual integer.
(define_expand "fixuns_trunctfsi2"
[(set (match_operand:SI 0 "register_operand" "")
(unsigned_fix:SI (match_operand:TF 1 "general_operand" "")))]
- "TARGET_FPU && TARGET_ARCH64 && ! TARGET_HARD_QUAD"
+ "TARGET_FPU && TARGET_ARCH64 && !TARGET_HARD_QUAD"
"emit_tfmode_cvt (UNSIGNED_FIX, operands); DONE;")
;; Now the same, for V9 targets
(define_expand "fixuns_trunctfdi2"
[(set (match_operand:DI 0 "register_operand" "")
(unsigned_fix:DI (match_operand:TF 1 "general_operand" "")))]
- "TARGET_FPU && TARGET_ARCH64 && ! TARGET_HARD_QUAD"
+ "TARGET_FPU && TARGET_ARCH64 && !TARGET_HARD_QUAD"
"emit_tfmode_cvt (UNSIGNED_FIX, operands); DONE;")
(match_operand:DI 2 "arith_double_add_operand" "")))]
""
{
- if (!TARGET_ARCH64)
+ if (TARGET_ARCH32)
{
emit_insn (gen_adddi3_sp32 (operands[0], operands[1], operands[2]));
DONE;
(pc)))]
""
{
- if (!TARGET_64BIT)
+ if (TARGET_ARCH32)
{
emit_insn (gen_uaddvdi4_sp32 (operands[0], operands[1], operands[2]));
rtx x = gen_rtx_LTU (VOIDmode, gen_rtx_REG (CCCmode, SPARC_ICC_REG),
(pc)))]
""
{
- if (!TARGET_64BIT)
+ if (TARGET_ARCH32)
{
emit_insn (gen_addvdi4_sp32 (operands[0], operands[1], operands[2]));
rtx x = gen_rtx_NE (VOIDmode, gen_rtx_REG (CCVmode, SPARC_ICC_REG),
(plus:DI (match_operand:DI 1 "register_operand" "%r")
(match_operand:DI 2 "arith_double_operand" "rHI")))
(clobber (reg:CC CC_REG))]
- "!TARGET_ARCH64"
+ "TARGET_ARCH32"
"#"
"&& reload_completed"
[(parallel [(set (reg:CCC CC_REG)
(match_dup 1)))
(set (match_operand:DI 0 "register_operand" "=&r")
(plus:DI (match_dup 1) (match_dup 2)))]
- "!TARGET_ARCH64"
+ "TARGET_ARCH32"
"#"
"&& reload_completed"
[(parallel [(set (reg:CCC CC_REG)
(unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_ADDV)))
(set (match_operand:DI 0 "register_operand" "=&r")
(plus:DI (match_dup 1) (match_dup 2)))]
- "!TARGET_ARCH64"
+ "TARGET_ARCH32"
"#"
"&& reload_completed"
[(parallel [(set (reg:CCC CC_REG)
(match_operand:SI 1 "register_operand" "%r")
(match_operand:SI 2 "arith_operand" "rI"))
(ltu:SI (reg:CCC CC_REG) (const_int 0)))))]
- "! TARGET_ARCH64"
+ "TARGET_ARCH32"
"#"
"&& reload_completed"
[(set (match_dup 3) (plus:SI (plus:SI (match_dup 1) (match_dup 2))
(plus:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
(match_operand:DI 2 "register_operand" "r")))
(clobber (reg:CC CC_REG))]
- "! TARGET_ARCH64"
+ "TARGET_ARCH32"
"#"
"&& reload_completed"
[(parallel [(set (reg:CCC CC_REG)
(match_operand:DI 2 "arith_double_add_operand" "")))]
""
{
- if (!TARGET_ARCH64)
+ if (TARGET_ARCH32)
{
emit_insn (gen_subdi3_sp32 (operands[0], operands[1], operands[2]));
DONE;
DONE;
}
- if (!TARGET_64BIT)
+ if (TARGET_ARCH32)
{
emit_insn (gen_usubvdi4_sp32 (operands[0], operands[1], operands[2]));
rtx x = gen_rtx_LTU (VOIDmode, gen_rtx_REG (CCCmode, SPARC_ICC_REG),
(pc)))]
""
{
- if (!TARGET_64BIT)
+ if (TARGET_ARCH32)
{
emit_insn (gen_subvdi4_sp32 (operands[0], operands[1], operands[2]));
rtx x = gen_rtx_NE (VOIDmode, gen_rtx_REG (CCVmode, SPARC_ICC_REG),
(minus:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "arith_double_operand" "rHI")))
(clobber (reg:CC CC_REG))]
- "! TARGET_ARCH64"
+ "TARGET_ARCH32"
"#"
"&& reload_completed"
[(parallel [(set (reg:CC CC_REG)
(match_operand:DI 2 "arith_double_operand" "rHI")))
(set (match_operand:DI 0 "register_operand" "=&r")
(minus:DI (match_dup 1) (match_dup 2)))]
- "!TARGET_ARCH64"
+ "TARGET_ARCH32"
"#"
"&& reload_completed"
[(parallel [(set (reg:CC CC_REG)
(unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_SUBV)))
(set (match_operand:DI 0 "register_operand" "=&r")
(minus:DI (match_dup 1) (match_dup 2)))]
- "!TARGET_ARCH64"
+ "TARGET_ARCH32"
"#"
"&& reload_completed"
[(parallel [(set (reg:CC CC_REG)
(match_operand:SI 1 "register_or_zero_operand" "rJ")
(match_operand:SI 2 "arith_operand" "rI"))
(ltu:SI (reg:CCC CC_REG) (const_int 0)))))]
- "! TARGET_ARCH64"
+ "TARGET_ARCH32"
"#"
"&& reload_completed"
[(set (match_dup 3) (minus:SI (minus:SI (match_dup 1) (match_dup 2))
(minus:DI (match_operand:DI 1 "register_operand" "r")
(zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))
(clobber (reg:CC CC_REG))]
- "! TARGET_ARCH64"
+ "TARGET_ARCH32"
"#"
"&& reload_completed"
[(parallel [(set (reg:CC CC_REG)
(define_insn "*cmp_ccv_minus_sltu_set"
[(set (reg:CCV CC_REG)
- (compare:CCV (minus:SI (minus:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
- (match_operand:SI 2 "arith_operand" "rI"))
- (ltu:SI (reg:CC CC_REG) (const_int 0)))
- (unspec:SI [(minus:SI (match_dup 1) (match_dup 2))
- (ltu:SI (reg:CC CC_REG) (const_int 0))]
- UNSPEC_SUBV)))
+ (compare:CCV
+ (minus:SI (minus:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
+ (match_operand:SI 2 "arith_operand" "rI"))
+ (ltu:SI (reg:CC CC_REG) (const_int 0)))
+ (unspec:SI [(minus:SI (match_dup 1) (match_dup 2))
+ (ltu:SI (reg:CC CC_REG) (const_int 0))]
+ UNSPEC_SUBV)))
(set (match_operand:SI 0 "register_operand" "=r")
(minus:SI (minus:SI (match_dup 1) (match_dup 2))
(ltu:SI (reg:CC CC_REG) (const_int 0))))]
(clobber (match_scratch:SI 3 "=&h,X"))
(clobber (match_scratch:SI 4 "=&h,X"))]
"TARGET_V8PLUS"
- "* return output_v8plus_mult (insn, operands, \"mulx\");"
+{
+ return output_v8plus_mult (insn, operands, \"mulx\");
+}
[(set_attr "type" "multi")
(set_attr "length" "9,8")])
(define_expand "smulsi3_highpart"
[(set (match_operand:SI 0 "register_operand" "")
(truncate:SI
- (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
- (sign_extend:DI (match_operand:SI 2 "arith_operand" "")))
- (const_int 32))))]
+ (lshiftrt:DI
+ (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
+ (sign_extend:DI (match_operand:SI 2 "arith_operand" "")))
+ (const_int 32))))]
"TARGET_HARD_MUL && TARGET_ARCH32"
{
if (CONSTANT_P (operands[2]))
(define_insn "smulsi3_highpart_v8plus"
[(set (match_operand:SI 0 "register_operand" "=h,r")
(truncate:SI
- (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
- (sign_extend:DI (match_operand:SI 2 "register_operand" "r,r")))
- (match_operand:SI 3 "small_int_operand" "I,I"))))
+ (lshiftrt:DI
+ (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
+ (sign_extend:DI (match_operand:SI 2 "register_operand" "r,r")))
+ (match_operand:SI 3 "small_int_operand" "I,I"))))
(clobber (match_scratch:SI 4 "=X,&h"))]
"TARGET_V8PLUS"
"@
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=h,r")
(subreg:SI
- (lshiftrt:DI
- (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
- (sign_extend:DI (match_operand:SI 2 "register_operand" "r,r")))
- (match_operand:SI 3 "small_int_operand" "I,I"))
- 4))
+ (lshiftrt:DI
+ (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
+ (sign_extend:DI (match_operand:SI 2 "register_operand" "r,r")))
+ (match_operand:SI 3 "small_int_operand" "I,I")) 4))
(clobber (match_scratch:SI 4 "=X,&h"))]
"TARGET_V8PLUS"
"@
(define_insn "const_smulsi3_highpart_v8plus"
[(set (match_operand:SI 0 "register_operand" "=h,r")
(truncate:SI
- (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
- (match_operand:DI 2 "small_int_operand" "I,I"))
- (match_operand:SI 3 "small_int_operand" "I,I"))))
+ (lshiftrt:DI
+ (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
+ (match_operand:DI 2 "small_int_operand" "I,I"))
+ (match_operand:SI 3 "small_int_operand" "I,I"))))
(clobber (match_scratch:SI 4 "=X,&h"))]
"TARGET_V8PLUS"
"@
(define_insn "*smulsi3_highpart_sp32"
[(set (match_operand:SI 0 "register_operand" "=r")
(truncate:SI
- (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
- (sign_extend:DI (match_operand:SI 2 "register_operand" "r")))
- (const_int 32))))]
+ (lshiftrt:DI
+ (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
+ (sign_extend:DI (match_operand:SI 2 "register_operand" "r")))
+ (const_int 32))))]
"TARGET_HARD_MUL32"
"smul\t%1, %2, %%g0\n\trd\t%%y, %0"
[(set_attr "type" "multi")
(define_insn "const_smulsi3_highpart"
[(set (match_operand:SI 0 "register_operand" "=r")
(truncate:SI
- (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
- (match_operand:DI 2 "small_int_operand" "i"))
- (const_int 32))))]
+ (lshiftrt:DI
+ (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
+ (match_operand:DI 2 "small_int_operand" "i"))
+ (const_int 32))))]
"TARGET_HARD_MUL32"
"smul\t%1, %2, %%g0\n\trd\t%%y, %0"
[(set_attr "type" "multi")
(define_expand "umulsi3_highpart"
[(set (match_operand:SI 0 "register_operand" "")
(truncate:SI
- (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
- (zero_extend:DI (match_operand:SI 2 "uns_arith_operand" "")))
- (const_int 32))))]
+ (lshiftrt:DI
+ (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
+ (zero_extend:DI (match_operand:SI 2 "uns_arith_operand" "")))
+ (const_int 32))))]
"TARGET_HARD_MUL && TARGET_ARCH32"
{
if (CONSTANT_P (operands[2]))
(define_insn "umulsi3_highpart_v8plus"
[(set (match_operand:SI 0 "register_operand" "=h,r")
(truncate:SI
- (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
- (zero_extend:DI (match_operand:SI 2 "register_operand" "r,r")))
- (match_operand:SI 3 "small_int_operand" "I,I"))))
+ (lshiftrt:DI
+ (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
+ (zero_extend:DI (match_operand:SI 2 "register_operand" "r,r")))
+ (match_operand:SI 3 "small_int_operand" "I,I"))))
(clobber (match_scratch:SI 4 "=X,h"))]
"TARGET_V8PLUS"
"@
(define_insn "const_umulsi3_highpart_v8plus"
[(set (match_operand:SI 0 "register_operand" "=h,r")
(truncate:SI
- (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
- (match_operand:DI 2 "uns_small_int_operand" ""))
- (match_operand:SI 3 "small_int_operand" "I,I"))))
+ (lshiftrt:DI
+ (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
+ (match_operand:DI 2 "uns_small_int_operand" ""))
+ (match_operand:SI 3 "small_int_operand" "I,I"))))
(clobber (match_scratch:SI 4 "=X,h"))]
"TARGET_V8PLUS"
"@
(define_insn "*umulsi3_highpart_sp32"
[(set (match_operand:SI 0 "register_operand" "=r")
(truncate:SI
- (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
- (zero_extend:DI (match_operand:SI 2 "register_operand" "r")))
- (const_int 32))))]
+ (lshiftrt:DI
+ (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
+ (zero_extend:DI (match_operand:SI 2 "register_operand" "r")))
+ (const_int 32))))]
"TARGET_HARD_MUL32"
"umul\t%1, %2, %%g0\n\trd\t%%y, %0"
[(set_attr "type" "multi")
(define_insn "const_umulsi3_highpart"
[(set (match_operand:SI 0 "register_operand" "=r")
(truncate:SI
- (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
- (match_operand:DI 2 "uns_small_int_operand" ""))
- (const_int 32))))]
+ (lshiftrt:DI
+ (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
+ (match_operand:DI 2 "uns_small_int_operand" ""))
+ (const_int 32))))]
"TARGET_HARD_MUL32"
"umul\t%1, %s2, %%g0\n\trd\t%%y, %0"
[(set_attr "type" "multi")
(define_expand "umulxhi_vis"
[(set (match_operand:DI 0 "register_operand" "")
- (truncate:DI
- (lshiftrt:TI
- (mult:TI (zero_extend:TI
- (match_operand:DI 1 "arith_operand" ""))
- (zero_extend:TI
- (match_operand:DI 2 "arith_operand" "")))
- (const_int 64))))]
+ (truncate:DI
+ (lshiftrt:TI
+ (mult:TI (zero_extend:TI (match_operand:DI 1 "arith_operand" ""))
+ (zero_extend:TI (match_operand:DI 2 "arith_operand" "")))
+ (const_int 64))))]
"TARGET_VIS3"
{
- if (! TARGET_ARCH64)
+ if (TARGET_ARCH32)
{
emit_insn (gen_umulxhi_v8plus (operands[0], operands[1], operands[2]));
DONE;
(define_insn "*umulxhi_sp64"
[(set (match_operand:DI 0 "register_operand" "=r")
- (truncate:DI
- (lshiftrt:TI
- (mult:TI (zero_extend:TI
- (match_operand:DI 1 "arith_operand" "%r"))
- (zero_extend:TI
- (match_operand:DI 2 "arith_operand" "rI")))
- (const_int 64))))]
+ (truncate:DI
+ (lshiftrt:TI
+ (mult:TI (zero_extend:TI (match_operand:DI 1 "arith_operand" "%r"))
+ (zero_extend:TI (match_operand:DI 2 "arith_operand" "rI")))
+ (const_int 64))))]
"TARGET_VIS3 && TARGET_ARCH64"
"umulxhi\t%1, %2, %0"
[(set_attr "type" "imul")])
(define_insn "umulxhi_v8plus"
[(set (match_operand:DI 0 "register_operand" "=r,h")
- (truncate:DI
- (lshiftrt:TI
- (mult:TI (zero_extend:TI
- (match_operand:DI 1 "arith_operand" "%r,0"))
- (zero_extend:TI
- (match_operand:DI 2 "arith_operand" "rI,rI")))
- (const_int 64))))
+ (truncate:DI
+ (lshiftrt:TI
+ (mult:TI (zero_extend:TI (match_operand:DI 1 "arith_operand" "%r,0"))
+ (zero_extend:TI (match_operand:DI 2 "arith_operand" "rI,rI")))
+ (const_int 64))))
(clobber (match_scratch:SI 3 "=&h,X"))
(clobber (match_scratch:SI 4 "=&h,X"))]
- "TARGET_VIS3 && ! TARGET_ARCH64"
- "* return output_v8plus_mult (insn, operands, \"umulxhi\");"
+ "TARGET_VIS3 && TARGET_ARCH32"
+{
+ return output_v8plus_mult (insn, operands, \"umulxhi\");
+}
[(set_attr "type" "imul")
(set_attr "length" "9,8")])
(define_expand "xmulx_vis"
[(set (match_operand:DI 0 "register_operand" "")
- (truncate:DI
- (unspec:TI [(zero_extend:TI
- (match_operand:DI 1 "arith_operand" ""))
- (zero_extend:TI
- (match_operand:DI 2 "arith_operand" ""))]
- UNSPEC_XMUL)))]
+ (truncate:DI
+ (unspec:TI [(zero_extend:TI (match_operand:DI 1 "arith_operand" ""))
+ (zero_extend:TI (match_operand:DI 2 "arith_operand" ""))]
+ UNSPEC_XMUL)))]
"TARGET_VIS3"
{
- if (! TARGET_ARCH64)
+ if (TARGET_ARCH32)
{
emit_insn (gen_xmulx_v8plus (operands[0], operands[1], operands[2]));
DONE;
(define_insn "*xmulx_sp64"
[(set (match_operand:DI 0 "register_operand" "=r")
- (truncate:DI
- (unspec:TI [(zero_extend:TI
- (match_operand:DI 1 "arith_operand" "%r"))
- (zero_extend:TI
- (match_operand:DI 2 "arith_operand" "rI"))]
- UNSPEC_XMUL)))]
+ (truncate:DI
+ (unspec:TI [(zero_extend:TI (match_operand:DI 1 "arith_operand" "%r"))
+ (zero_extend:TI (match_operand:DI 2 "arith_operand" "rI"))]
+ UNSPEC_XMUL)))]
"TARGET_VIS3 && TARGET_ARCH64"
"xmulx\t%1, %2, %0"
[(set_attr "type" "imul")])
(define_insn "xmulx_v8plus"
[(set (match_operand:DI 0 "register_operand" "=r,h")
- (truncate:DI
- (unspec:TI [(zero_extend:TI
- (match_operand:DI 1 "arith_operand" "%r,0"))
- (zero_extend:TI
- (match_operand:DI 2 "arith_operand" "rI,rI"))]
- UNSPEC_XMUL)))
+ (truncate:DI
+ (unspec:TI [(zero_extend:TI (match_operand:DI 1 "arith_operand" "%r,0"))
+ (zero_extend:TI (match_operand:DI 2 "arith_operand" "rI,rI"))]
+ UNSPEC_XMUL)))
(clobber (match_scratch:SI 3 "=&h,X"))
(clobber (match_scratch:SI 4 "=&h,X"))]
- "TARGET_VIS3 && ! TARGET_ARCH64"
- "* return output_v8plus_mult (insn, operands, \"xmulx\");"
+ "TARGET_VIS3 && TARGET_ARCH32"
+{
+ return output_v8plus_mult (insn, operands, \"xmulx\");
+}
[(set_attr "type" "imul")
(set_attr "length" "9,8")])
(define_expand "xmulxhi_vis"
[(set (match_operand:DI 0 "register_operand" "")
- (truncate:DI
- (lshiftrt:TI
- (unspec:TI [(zero_extend:TI
- (match_operand:DI 1 "arith_operand" ""))
- (zero_extend:TI
- (match_operand:DI 2 "arith_operand" ""))]
- UNSPEC_XMUL)
- (const_int 64))))]
+ (truncate:DI
+ (lshiftrt:TI
+ (unspec:TI [(zero_extend:TI (match_operand:DI 1 "arith_operand" ""))
+ (zero_extend:TI (match_operand:DI 2 "arith_operand" ""))]
+ UNSPEC_XMUL)
+ (const_int 64))))]
"TARGET_VIS3"
{
- if (! TARGET_ARCH64)
+ if (TARGET_ARCH32)
{
emit_insn (gen_xmulxhi_v8plus (operands[0], operands[1], operands[2]));
DONE;
(define_insn "*xmulxhi_sp64"
[(set (match_operand:DI 0 "register_operand" "=r")
- (truncate:DI
- (lshiftrt:TI
- (unspec:TI [(zero_extend:TI
- (match_operand:DI 1 "arith_operand" "%r"))
- (zero_extend:TI
- (match_operand:DI 2 "arith_operand" "rI"))]
- UNSPEC_XMUL)
- (const_int 64))))]
+ (truncate:DI
+ (lshiftrt:TI
+ (unspec:TI [(zero_extend:TI (match_operand:DI 1 "arith_operand" "%r"))
+ (zero_extend:TI (match_operand:DI 2 "arith_operand" "rI"))]
+ UNSPEC_XMUL)
+ (const_int 64))))]
"TARGET_VIS3 && TARGET_ARCH64"
"xmulxhi\t%1, %2, %0"
[(set_attr "type" "imul")])
(define_insn "xmulxhi_v8plus"
[(set (match_operand:DI 0 "register_operand" "=r,h")
- (truncate:DI
- (lshiftrt:TI
- (unspec:TI [(zero_extend:TI
- (match_operand:DI 1 "arith_operand" "%r,0"))
- (zero_extend:TI
- (match_operand:DI 2 "arith_operand" "rI,rI"))]
- UNSPEC_XMUL)
- (const_int 64))))
+ (truncate:DI
+ (lshiftrt:TI
+ (unspec:TI [(zero_extend:TI (match_operand:DI 1 "arith_operand" "%r,0"))
+ (zero_extend:TI (match_operand:DI 2 "arith_operand" "rI,rI"))]
+ UNSPEC_XMUL)
+ (const_int 64))))
(clobber (match_scratch:SI 3 "=&h,X"))
(clobber (match_scratch:SI 4 "=&h,X"))]
- "TARGET_VIS3 && !TARGET_ARCH64"
- "* return output_v8plus_mult (insn, operands, \"xmulxhi\");"
+ "TARGET_VIS3 && TARGET_ARCH32"
+{
+ return output_v8plus_mult (insn, operands, \"xmulxhi\");
+}
[(set_attr "type" "imul")
(set_attr "length" "9,8")])
(define_insn "*cmp_cc_arith_op"
[(set (reg:CC CC_REG)
- (compare:CC
- (match_operator:SI 2 "cc_arith_operator"
- [(match_operand:SI 0 "arith_operand" "%r")
- (match_operand:SI 1 "arith_operand" "rI")])
+ (compare:CC (match_operator:SI 2 "cc_arith_operator"
+ [(match_operand:SI 0 "arith_operand" "%r")
+ (match_operand:SI 1 "arith_operand" "rI")])
(const_int 0)))]
""
"%A2cc\t%0, %1, %%g0"
(define_insn "*cmp_ccx_arith_op"
[(set (reg:CCX CC_REG)
- (compare:CCX
- (match_operator:DI 2 "cc_arith_operator"
- [(match_operand:DI 0 "arith_operand" "%r")
- (match_operand:DI 1 "arith_operand" "rI")])
+ (compare:CCX (match_operator:DI 2 "cc_arith_operator"
+ [(match_operand:DI 0 "arith_operand" "%r")
+ (match_operand:DI 1 "arith_operand" "rI")])
(const_int 0)))]
"TARGET_ARCH64"
"%A2cc\t%0, %1, %%g0"
(define_insn "*cmp_cc_arith_op_set"
[(set (reg:CC CC_REG)
- (compare:CC
- (match_operator:SI 3 "cc_arith_operator"
- [(match_operand:SI 1 "arith_operand" "%r")
- (match_operand:SI 2 "arith_operand" "rI")])
+ (compare:CC (match_operator:SI 3 "cc_arith_operator"
+ [(match_operand:SI 1 "arith_operand" "%r")
+ (match_operand:SI 2 "arith_operand" "rI")])
(const_int 0)))
(set (match_operand:SI 0 "register_operand" "=r")
- (match_operator:SI 4 "cc_arith_operator" [(match_dup 1) (match_dup 2)]))]
+ (match_operator:SI 4 "cc_arith_operator"
+ [(match_dup 1) (match_dup 2)]))]
"GET_CODE (operands[3]) == GET_CODE (operands[4])"
"%A3cc\t%1, %2, %0"
[(set_attr "type" "compare")])
(define_insn "*cmp_ccx_arith_op_set"
[(set (reg:CCX CC_REG)
- (compare:CCX
- (match_operator:DI 3 "cc_arith_operator"
- [(match_operand:DI 1 "arith_operand" "%r")
- (match_operand:DI 2 "arith_operand" "rI")])
+ (compare:CCX (match_operator:DI 3 "cc_arith_operator"
+ [(match_operand:DI 1 "arith_operand" "%r")
+ (match_operand:DI 2 "arith_operand" "rI")])
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=r")
- (match_operator:DI 4 "cc_arith_operator" [(match_dup 1) (match_dup 2)]))]
+ (match_operator:DI 4 "cc_arith_operator"
+ [(match_dup 1) (match_dup 2)]))]
"TARGET_ARCH64 && GET_CODE (operands[3]) == GET_CODE (operands[4])"
"%A3cc\t%1, %2, %0"
[(set_attr "type" "compare")])
(define_insn "*cmp_cc_arith_op_not"
[(set (reg:CC CC_REG)
- (compare:CC
- (match_operator:SI 2 "cc_arith_not_operator"
- [(not:SI (match_operand:SI 0 "arith_operand" "rI"))
- (match_operand:SI 1 "register_or_zero_operand" "rJ")])
+ (compare:CC (match_operator:SI 2 "cc_arith_not_operator"
+ [(not:SI (match_operand:SI 0 "arith_operand" "rI"))
+ (match_operand:SI 1 "register_or_zero_operand" "rJ")])
(const_int 0)))]
""
"%B2cc\t%r1, %0, %%g0"
(define_insn "*cmp_ccx_arith_op_not"
[(set (reg:CCX CC_REG)
- (compare:CCX
- (match_operator:DI 2 "cc_arith_not_operator"
- [(not:DI (match_operand:DI 0 "arith_operand" "rI"))
- (match_operand:DI 1 "register_or_zero_operand" "rJ")])
+ (compare:CCX (match_operator:DI 2 "cc_arith_not_operator"
+ [(not:DI (match_operand:DI 0 "arith_operand" "rI"))
+ (match_operand:DI 1 "register_or_zero_operand" "rJ")])
(const_int 0)))]
"TARGET_ARCH64"
"%B2cc\t%r1, %0, %%g0"
(define_insn "*cmp_cc_arith_op_not_set"
[(set (reg:CC CC_REG)
- (compare:CC
- (match_operator:SI 3 "cc_arith_not_operator"
- [(not:SI (match_operand:SI 1 "arith_operand" "rI"))
- (match_operand:SI 2 "register_or_zero_operand" "rJ")])
+ (compare:CC (match_operator:SI 3 "cc_arith_not_operator"
+ [(not:SI (match_operand:SI 1 "arith_operand" "rI"))
+ (match_operand:SI 2 "register_or_zero_operand" "rJ")])
(const_int 0)))
(set (match_operand:SI 0 "register_operand" "=r")
(match_operator:SI 4 "cc_arith_not_operator"
- [(not:SI (match_dup 1)) (match_dup 2)]))]
+ [(not:SI (match_dup 1)) (match_dup 2)]))]
"GET_CODE (operands[3]) == GET_CODE (operands[4])"
"%B3cc\t%r2, %1, %0"
[(set_attr "type" "compare")])
(define_insn "*cmp_ccx_arith_op_not_set"
[(set (reg:CCX CC_REG)
- (compare:CCX
- (match_operator:DI 3 "cc_arith_not_operator"
- [(not:DI (match_operand:DI 1 "arith_operand" "rI"))
- (match_operand:DI 2 "register_or_zero_operand" "rJ")])
+ (compare:CCX (match_operator:DI 3 "cc_arith_not_operator"
+ [(not:DI (match_operand:DI 1 "arith_operand" "rI"))
+ (match_operand:DI 2 "register_or_zero_operand" "rJ")])
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=r")
(match_operator:DI 4 "cc_arith_not_operator"
- [(not:DI (match_dup 1)) (match_dup 2)]))]
+ [(not:DI (match_dup 1)) (match_dup 2)]))]
"TARGET_ARCH64 && GET_CODE (operands[3]) == GET_CODE (operands[4])"
"%B3cc\t%r2, %1, %0"
[(set_attr "type" "compare")])
(neg:DI (match_operand:DI 1 "register_operand" "r")))]
""
{
- if (!TARGET_ARCH64)
+ if (TARGET_ARCH32)
{
emit_insn (gen_negdi2_sp32 (operands[0], operands[1]));
DONE;
(pc)))]
""
{
- if (!TARGET_64BIT)
+ if (TARGET_ARCH32)
{
emit_insn (gen_unegvdi3_sp32 (operands[0], operands[1]));
rtx x = gen_rtx_LTU (VOIDmode, gen_rtx_REG (CCCmode, SPARC_ICC_REG),
(pc)))]
""
{
- if (!TARGET_64BIT)
+ if (TARGET_ARCH32)
{
emit_insn (gen_negvdi3_sp32 (operands[0], operands[1]));
rtx x = gen_rtx_NE (VOIDmode, gen_rtx_REG (CCVmode, SPARC_ICC_REG),
[(set (match_operand:DI 0 "register_operand" "=&r")
(neg:DI (match_operand:DI 1 "register_operand" "r")))
(clobber (reg:CC CC_REG))]
- "! TARGET_ARCH64"
+ "TARGET_ARCH32"
"#"
"&& reload_completed"
[(parallel [(set (reg:CCC CC_REG)
(const_int -1)))
(set (match_operand:DI 0 "register_operand" "=&r")
(neg:DI (match_dup 1)))]
- "!TARGET_ARCH64"
+ "TARGET_ARCH32"
"#"
"&& reload_completed"
[(parallel [(set (reg:CCC CC_REG)
(unspec:DI [(match_dup 1)] UNSPEC_NEGV)))
(set (match_operand:DI 0 "register_operand" "=&r")
(neg:DI (match_dup 1)))]
- "!TARGET_ARCH64"
+ "TARGET_ARCH32"
"#"
"&& reload_completed"
[(parallel [(set (reg:CCC CC_REG)
(match_operand:SI 2 "arith_operand" "rI")))]
"TARGET_ARCH64 || TARGET_V8PLUS"
{
- if (! TARGET_ARCH64)
+ if (TARGET_ARCH32)
{
if (GET_CODE (operands[2]) == CONST_INT)
FAIL;
(match_operand:SI 2 "arith_operand" "rI,rI,rI")))
(clobber (match_scratch:SI 3 "=X,X,&h"))]
"TARGET_V8PLUS"
- "* return output_v8plus_shift (insn ,operands, \"sllx\");"
+{
+ return output_v8plus_shift (insn ,operands, \"sllx\");
+}
[(set_attr "type" "multi")
(set_attr "length" "5,5,6")])
(ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "arith_operand" "rI")))]
""
- {
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
- return "sra\t%1, %2, %0";
- }
+{
+ if (GET_CODE (operands[2]) == CONST_INT)
+ operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
+ return "sra\t%1, %2, %0";
+}
[(set_attr "type" "shift")])
(define_insn "*ashrsi3_extend"
(match_operand:SI 2 "arith_operand" "rI")))]
"TARGET_ARCH64 || TARGET_V8PLUS"
{
- if (! TARGET_ARCH64)
+ if (TARGET_ARCH32)
{
if (GET_CODE (operands[2]) == CONST_INT)
FAIL; /* prefer generic code in this case */
(ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:SI 2 "arith_operand" "rI")))]
"TARGET_ARCH64"
-
- {
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
- return "srax\t%1, %2, %0";
- }
+{
+ if (GET_CODE (operands[2]) == CONST_INT)
+ operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
+ return "srax\t%1, %2, %0";
+}
[(set_attr "type" "shift")])
(define_insn "ashrdi3_v8plus"
(match_operand:SI 2 "arith_operand" "rI,rI,rI")))
(clobber (match_scratch:SI 3 "=X,X,&h"))]
"TARGET_V8PLUS"
- "* return output_v8plus_shift (insn, operands, \"srax\");"
+{
+ return output_v8plus_shift (insn, operands, \"srax\");
+}
[(set_attr "type" "multi")
(set_attr "length" "5,5,6")])
(lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "arith_operand" "rI")))]
""
- {
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
- return "srl\t%1, %2, %0";
- }
+{
+ if (GET_CODE (operands[2]) == CONST_INT)
+ operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
+ return "srl\t%1, %2, %0";
+}
[(set_attr "type" "shift")])
(define_insn "*lshrsi3_extend0"
(lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "arith_operand" "rI"))))]
"TARGET_ARCH64"
- {
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
- return "srl\t%1, %2, %0";
- }
+{
+ if (GET_CODE (operands[2]) == CONST_INT)
+ operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
+ return "srl\t%1, %2, %0";
+}
[(set_attr "type" "shift")])
;; This handles the case where
(match_operand:SI 2 "arith_operand" "rI")))]
"TARGET_ARCH64 || TARGET_V8PLUS"
{
- if (! TARGET_ARCH64)
+ if (TARGET_ARCH32)
{
if (GET_CODE (operands[2]) == CONST_INT)
FAIL;
(lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:SI 2 "arith_operand" "rI")))]
"TARGET_ARCH64"
- {
- if (GET_CODE (operands[2]) == CONST_INT)
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
- return "srlx\t%1, %2, %0";
- }
+{
+ if (GET_CODE (operands[2]) == CONST_INT)
+ operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
+ return "srlx\t%1, %2, %0";
+}
[(set_attr "type" "shift")])
(define_insn "lshrdi3_v8plus"
(match_operand:SI 2 "arith_operand" "rI,rI,rI")))
(clobber (match_scratch:SI 3 "=X,X,&h"))]
"TARGET_V8PLUS"
- "* return output_v8plus_shift (insn, operands, \"srlx\");"
+{
+ return output_v8plus_shift (insn, operands, \"srlx\");
+}
[(set_attr "type" "multi")
(set_attr "length" "5,5,6")])
(define_insn "*jump_ubranch"
[(set (pc) (label_ref (match_operand 0 "" "")))]
- "! TARGET_CBCOND"
- "* return output_ubranch (operands[0], insn);"
+ "!TARGET_CBCOND"
+{
+ return output_ubranch (operands[0], insn);
+}
[(set_attr "type" "uncond_branch")])
(define_insn "*jump_cbcond"
[(set (pc) (label_ref (match_operand 0 "" "")))]
"TARGET_CBCOND"
- "* return output_ubranch (operands[0], insn);"
+{
+ return output_ubranch (operands[0], insn);
+}
[(set_attr "type" "uncond_cbcond")])
(define_expand "tablejump"
(define_insn "*tablejump_sp32"
[(set (pc) (match_operand:SI 0 "address_operand" "p"))
(use (label_ref (match_operand 1 "" "")))]
- "! TARGET_ARCH64"
+ "TARGET_ARCH32"
"jmp\t%a0%#"
[(set_attr "type" "uncond_branch")])
Why cannot we have delay slots filled if it were a CALL? */
/* We accept negative sizes for untyped calls. */
- if (! TARGET_ARCH64 && INTVAL (operands[3]) != 0)
+ if (TARGET_ARCH32 && INTVAL (operands[3]) != 0)
emit_jump_insn
(gen_rtx_PARALLEL
(VOIDmode,
fn_rtx = operands[0];
/* We accept negative sizes for untyped calls. */
- if (! TARGET_ARCH64 && INTVAL (operands[3]) != 0)
+ if (TARGET_ARCH32 && INTVAL (operands[3]) != 0)
sparc_emit_call_insn
(gen_rtx_PARALLEL
(VOIDmode,
(match_operand 1 "" ""))
(clobber (reg:SI O7_REG))]
;;- Do not use operand 1 for most machines.
- "! TARGET_ARCH64"
+ "TARGET_ARCH32"
"call\t%a0, %1%#"
[(set_attr "type" "call")])
(match_operand 1 "" ""))
(clobber (reg:SI O7_REG))]
;;- Do not use operand 1 for most machines.
- "! TARGET_ARCH64"
+ "TARGET_ARCH32"
"call\t%a0, %1%#"
[(set_attr "type" "call")])
(match_operand 2 "immediate_operand" "")
(clobber (reg:SI O7_REG))]
;;- Do not use operand 1 for most machines.
- "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 0"
+ "TARGET_ARCH32 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 0"
{
operands[2] = GEN_INT (INTVAL (operands[2]) & 0xfff);
return "call\t%a0, %1\n\t nop\n\tunimp\t%2";
(match_operand 2 "immediate_operand" "")
(clobber (reg:SI O7_REG))]
;;- Do not use operand 1 for most machines.
- "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 0"
+ "TARGET_ARCH32 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 0"
{
operands[2] = GEN_INT (INTVAL (operands[2]) & 0xfff);
return "call\t%a0, %1\n\t nop\n\tunimp\t%2";
(match_operand 2 "immediate_operand" "")
(clobber (reg:SI O7_REG))]
;;- Do not use operand 1 for most machines.
- "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0"
+ "TARGET_ARCH32 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0"
"call\t%a0, %1\n\t nop\n\tnop"
[(set_attr "type" "call_no_delay_slot")
(set_attr "length" "3")])
(match_operand 2 "immediate_operand" "")
(clobber (reg:SI O7_REG))]
;;- Do not use operand 1 for most machines.
- "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0"
+ "TARGET_ARCH32 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0"
"call\t%a0, %1\n\t nop\n\tnop"
[(set_attr "type" "call_no_delay_slot")
(set_attr "length" "3")])
(match_operand 2 "" "")))
(clobber (reg:SI O7_REG))]
;;- Do not use operand 2 for most machines.
- "! TARGET_ARCH64"
+ "TARGET_ARCH32"
"call\t%a1, %2%#"
[(set_attr "type" "call")])
(match_operand 2 "" "")))
(clobber (reg:SI O7_REG))]
;;- Do not use operand 2 for most machines.
- "! TARGET_ARCH64"
+ "TARGET_ARCH32"
"call\t%a1, %2%#"
[(set_attr "type" "call")])
[(call (mem:SI (match_operand:SI 0 "symbolic_operand" "s"))
(match_operand 1 "" ""))
(return)]
- "! TARGET_ARCH64"
- "* return output_sibcall(insn, operands[0]);"
+ "TARGET_ARCH32"
+{
+ return output_sibcall(insn, operands[0]);
+}
[(set_attr "type" "sibcall")])
(define_insn "*sibcall_symbolic_sp64"
(match_operand 1 "" ""))
(return)]
"TARGET_ARCH64"
- "* return output_sibcall(insn, operands[0]);"
+{
+ return output_sibcall(insn, operands[0]);
+}
[(set_attr "type" "sibcall")])
(define_expand "sibcall_value"
(call (mem:SI (match_operand:SI 1 "symbolic_operand" "s"))
(match_operand 2 "" "")))
(return)]
- "! TARGET_ARCH64"
- "* return output_sibcall(insn, operands[1]);"
+ "TARGET_ARCH32"
+{
+ return output_sibcall(insn, operands[1]);
+}
[(set_attr "type" "sibcall")])
(define_insn "*sibcall_value_symbolic_sp64"
(match_operand 2 "" "")))
(return)]
"TARGET_ARCH64"
- "* return output_sibcall(insn, operands[1]);"
+{
+ return output_sibcall(insn, operands[1]);
+}
[(set_attr "type" "sibcall")])
(define_insn "*return_internal"
[(return)]
""
- "* return output_return (insn);"
+{
+ return output_return (insn);
+}
[(set_attr "type" "return")
(set (attr "length")
(cond [(eq_attr "calls_eh_return" "true")
(match_operand:P 2 "register_operand" "r")]
UNSPECV_PROBE_STACK_RANGE))]
""
- "* return output_probe_stack_range (operands[0], operands[2]);"
+{
+ return output_probe_stack_range (operands[0], operands[2]);
+}
[(set_attr "type" "multi")])
;; Prepare to return any type including a structure value.
rtx valreg1 = gen_rtx_REG (DImode, 24);
rtx result = operands[0];
- if (! TARGET_ARCH64)
+ if (TARGET_ARCH32)
{
rtx rtnreg = gen_rtx_REG (SImode, RETURN_ADDR_REGNUM);
rtx value = gen_reg_rtx (SImode);
(define_insn "update_return"
[(unspec:SI [(match_operand:SI 0 "register_operand" "r")
(match_operand:SI 1 "register_operand" "r")] UNSPEC_UPDATE_RETURN)]
- "! TARGET_ARCH64"
+ "TARGET_ARCH32"
{
if (flag_delayed_branch)
return "cmp\t%1, 0\n\tbe,a\t.+8\n\t add\t%0, 4, %0";
(define_insn "*branch_sp32"
[(set (pc) (match_operand:SI 0 "address_operand" "p"))]
- "! TARGET_ARCH64"
+ "TARGET_ARCH32"
"jmp\t%a0%#"
[(set_attr "type" "uncond_branch")])
(define_insn "flush_register_windows"
[(unspec_volatile [(const_int 0)] UNSPECV_FLUSHW)]
""
- { return TARGET_V9 ? "flushw" : "ta\t3"; }
+{
+ return TARGET_V9 ? "flushw" : "ta\t3";
+}
[(set_attr "type" "flushw")])
;; Special pattern for the FLUSH instruction.
(define_insn "flush<P:mode>"
[(unspec_volatile [(match_operand:P 0 "memory_operand" "m")] UNSPECV_FLUSH)]
""
- { return TARGET_V9 ? "flush\t%f0" : "iflush\t%f0"; }
+{
+ return TARGET_V9 ? "flush\t%f0" : "iflush\t%f0";
+}
[(set_attr "type" "iflush")])
;; Special insns to load and store the 32-bit FP Status Register.
;; Find first set instructions.
-;; The scan instruction searches from the most significant bit while ffs
-;; searches from the least significant bit. The bit index and treatment of
-;; zero also differ. It takes at least 7 instructions to get the proper
-;; result. Here is an obvious 8 instruction sequence.
-
-;; XXX
-(define_insn "ffssi2"
- [(set (match_operand:SI 0 "register_operand" "=&r")
- (ffs:SI (match_operand:SI 1 "register_operand" "r")))
- (clobber (match_scratch:SI 2 "=&r"))]
- "TARGET_SPARCLITE || TARGET_SPARCLET"
-{
- return "sub\t%%g0, %1, %0\;and\t%0, %1, %0\;scan\t%0, 0, %0\;mov\t32, %2\;sub\t%2, %0, %0\;sra\t%0, 31, %2\;and\t%2, 31, %2\;add\t%2, %0, %0";
-}
- [(set_attr "type" "multi")
- (set_attr "length" "8")])
-
(define_expand "popcountdi2"
[(set (match_operand:DI 0 "register_operand" "")
(popcount:DI (match_operand:DI 1 "register_operand" "")))]
"TARGET_POPC"
{
- if (! TARGET_ARCH64)
+ if (TARGET_ARCH32)
{
emit_insn (gen_popcountdi_v8plus (operands[0], operands[1]));
DONE;
[(set (match_operand:DI 0 "register_operand" "=r")
(popcount:DI (match_operand:DI 1 "register_operand" "r")))
(clobber (match_scratch:SI 2 "=&h"))]
- "TARGET_POPC && ! TARGET_ARCH64"
+ "TARGET_POPC && TARGET_ARCH32"
{
if (sparc_check_64 (operands[1], insn) <= 0)
output_asm_insn ("srl\t%L1, 0, %L1", operands);
(truncate:SI (popcount:DI (match_dup 2))))]
"TARGET_POPC"
{
- if (! TARGET_ARCH64)
+ if (TARGET_ARCH32)
{
emit_insn (gen_popcountsi_v8plus (operands[0], operands[1]));
DONE;
(define_insn "popcountsi_v8plus"
[(set (match_operand:SI 0 "register_operand" "=r")
(popcount:SI (match_operand:SI 1 "register_operand" "r")))]
- "TARGET_POPC && ! TARGET_ARCH64"
+ "TARGET_POPC && TARGET_ARCH32"
{
if (sparc_check_64 (operands[1], insn) <= 0)
output_asm_insn ("srl\t%1, 0, %1", operands);
(clz:DI (match_operand:DI 1 "register_operand" "")))]
"TARGET_VIS3"
{
- if (! TARGET_ARCH64)
+ if (TARGET_ARCH32)
{
emit_insn (gen_clzdi_v8plus (operands[0], operands[1]));
DONE;
[(set (match_operand:DI 0 "register_operand" "=r")
(clz:DI (match_operand:DI 1 "register_operand" "r")))
(clobber (match_scratch:SI 2 "=&h"))]
- "TARGET_VIS3 && ! TARGET_ARCH64"
+ "TARGET_VIS3 && TARGET_ARCH32"
{
if (sparc_check_64 (operands[1], insn) <= 0)
output_asm_insn ("srl\t%L1, 0, %L1", operands);
(minus:SI (match_dup 3) (const_int 32)))]
"TARGET_VIS3"
{
- if (! TARGET_ARCH64)
+ if (TARGET_ARCH32)
{
emit_insn (gen_clzsi_v8plus (operands[0], operands[1]));
DONE;
(define_insn "clzsi_v8plus"
[(set (match_operand:SI 0 "register_operand" "=r")
(clz:SI (match_operand:SI 1 "register_operand" "r")))]
- "TARGET_VIS3 && ! TARGET_ARCH64"
+ "TARGET_VIS3 && TARGET_ARCH32"
{
if (sparc_check_64 (operands[1], insn) <= 0)
output_asm_insn ("srl\t%1, 0, %1", operands);
(const_int 0)))]
"(rtx_equal_p (operands[2], operands[0])
|| rtx_equal_p (operands[2], operands[1]))
- && ! SPARC_FP_REG_P (REGNO (operands[0]))
- && ! SPARC_FP_REG_P (REGNO (operands[1]))"
+ && !SPARC_FP_REG_P (REGNO (operands[0]))
+ && !SPARC_FP_REG_P (REGNO (operands[1]))"
[(parallel [(set (match_dup 0) (match_dup 1))
(set (reg:CC CC_REG)
(compare:CC (match_dup 1) (const_int 0)))])]
"TARGET_ARCH64
&& (rtx_equal_p (operands[2], operands[0])
|| rtx_equal_p (operands[2], operands[1]))
- && ! SPARC_FP_REG_P (REGNO (operands[0]))
- && ! SPARC_FP_REG_P (REGNO (operands[1]))"
+ && !SPARC_FP_REG_P (REGNO (operands[0]))
+ && !SPARC_FP_REG_P (REGNO (operands[1]))"
[(parallel [(set (match_dup 0) (match_dup 1))
(set (reg:CCX CC_REG)
(compare:CCX (match_dup 1) (const_int 0)))])]
;; Prefetch instructions.
-;; ??? UltraSPARC-III note: A memory operation loading into the floating point register
-;; ??? file, if it hits the prefetch cache, has a chance to dual-issue with other memory
-;; ??? operations. With DFA we might be able to model this, but it requires a lot of
-;; ??? state.
+;; ??? UltraSPARC-III note: A memory operation loading into the floating point
+;; register file, if it hits the prefetch cache, has a chance to dual-issue
+;; with other memory operations. With DFA we might be able to model this,
+;; but it requires a lot of state.
(define_expand "prefetch"
[(match_operand 0 "address_operand" "")
(match_operand 1 "const_int_operand" "")
[(trap_if (match_operator 0 "comparison_operator"
[(match_operand:SI 1 "compare_operand" "")
(match_operand:SI 2 "arith_operand" "")])
- (match_operand 3 "arith_operand"))]
+ (match_operand 3 "arith_operand"))]
""
{
operands[1] = gen_compare_reg (operands[0]);
[(trap_if (match_operator 0 "comparison_operator"
[(match_operand:DI 1 "compare_operand" "")
(match_operand:DI 2 "arith_operand" "")])
- (match_operand 3 "arith_operand"))]
+ (match_operand 3 "arith_operand"))]
"TARGET_ARCH64"
{
operands[1] = gen_compare_reg (operands[0]);
(define_insn "*trapsi_insn"
[(trap_if (match_operator 0 "icc_comparison_operator"
- [(reg:CC CC_REG) (const_int 0)])
+ [(reg:CC CC_REG) (const_int 0)])
(match_operand:SI 1 "arith_operand" "rM"))]
""
{
(define_insn "*trapdi_insn"
[(trap_if (match_operator 0 "icc_comparison_operator"
- [(reg:CCX CC_REG) (const_int 0)])
+ [(reg:CCX CC_REG) (const_int 0)])
(match_operand:SI 1 "arith_operand" "rM"))]
"TARGET_V9"
"t%C0\t%%xcc, %1"
(define_insn "*tldo_ldub1_sp32"
[(set (match_operand:HI 0 "register_operand" "=r")
- (zero_extend:HI (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
- (match_operand 3 "tld_symbolic_operand" "")]
- UNSPEC_TLSLDO)
- (match_operand:SI 1 "register_operand" "r")))))]
+ (zero_extend:HI
+ (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
+ (match_operand 3 "tld_symbolic_operand" "")]
+ UNSPEC_TLSLDO)
+ (match_operand:SI 1 "register_operand" "r")))))]
"TARGET_TLS && TARGET_ARCH32"
"ldub\t[%1 + %2], %0, %%tldo_add(%3)"
[(set_attr "type" "load")
(define_insn "*tldo_ldub2_sp32"
[(set (match_operand:SI 0 "register_operand" "=r")
- (zero_extend:SI (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
- (match_operand 3 "tld_symbolic_operand" "")]
- UNSPEC_TLSLDO)
- (match_operand:SI 1 "register_operand" "r")))))]
+ (zero_extend:SI
+ (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
+ (match_operand 3 "tld_symbolic_operand" "")]
+ UNSPEC_TLSLDO)
+ (match_operand:SI 1 "register_operand" "r")))))]
"TARGET_TLS && TARGET_ARCH32"
"ldub\t[%1 + %2], %0, %%tldo_add(%3)"
[(set_attr "type" "load")
(define_insn "*tldo_ldsb1_sp32"
[(set (match_operand:HI 0 "register_operand" "=r")
- (sign_extend:HI (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
- (match_operand 3 "tld_symbolic_operand" "")]
- UNSPEC_TLSLDO)
- (match_operand:SI 1 "register_operand" "r")))))]
+ (sign_extend:HI
+ (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
+ (match_operand 3 "tld_symbolic_operand" "")]
+ UNSPEC_TLSLDO)
+ (match_operand:SI 1 "register_operand" "r")))))]
"TARGET_TLS && TARGET_ARCH32"
"ldsb\t[%1 + %2], %0, %%tldo_add(%3)"
[(set_attr "type" "sload")
(define_insn "*tldo_ldsb2_sp32"
[(set (match_operand:SI 0 "register_operand" "=r")
- (sign_extend:SI (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
- (match_operand 3 "tld_symbolic_operand" "")]
- UNSPEC_TLSLDO)
- (match_operand:SI 1 "register_operand" "r")))))]
+ (sign_extend:SI
+ (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
+ (match_operand 3 "tld_symbolic_operand" "")]
+ UNSPEC_TLSLDO)
+ (match_operand:SI 1 "register_operand" "r")))))]
"TARGET_TLS && TARGET_ARCH32"
"ldsb\t[%1 + %2], %0, %%tldo_add(%3)"
[(set_attr "type" "sload")
(define_insn "*tldo_ldub1_sp64"
[(set (match_operand:HI 0 "register_operand" "=r")
- (zero_extend:HI (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
- (match_operand 3 "tld_symbolic_operand" "")]
- UNSPEC_TLSLDO)
- (match_operand:DI 1 "register_operand" "r")))))]
+ (zero_extend:HI
+ (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+ (match_operand 3 "tld_symbolic_operand" "")]
+ UNSPEC_TLSLDO)
+ (match_operand:DI 1 "register_operand" "r")))))]
"TARGET_TLS && TARGET_ARCH64"
"ldub\t[%1 + %2], %0, %%tldo_add(%3)"
[(set_attr "type" "load")
(define_insn "*tldo_ldub2_sp64"
[(set (match_operand:SI 0 "register_operand" "=r")
- (zero_extend:SI (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
- (match_operand 3 "tld_symbolic_operand" "")]
- UNSPEC_TLSLDO)
- (match_operand:DI 1 "register_operand" "r")))))]
+ (zero_extend:SI
+ (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+ (match_operand 3 "tld_symbolic_operand" "")]
+ UNSPEC_TLSLDO)
+ (match_operand:DI 1 "register_operand" "r")))))]
"TARGET_TLS && TARGET_ARCH64"
"ldub\t[%1 + %2], %0, %%tldo_add(%3)"
[(set_attr "type" "load")
(define_insn "*tldo_ldub3_sp64"
[(set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
- (match_operand 3 "tld_symbolic_operand" "")]
- UNSPEC_TLSLDO)
- (match_operand:DI 1 "register_operand" "r")))))]
+ (zero_extend:DI
+ (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+ (match_operand 3 "tld_symbolic_operand" "")]
+ UNSPEC_TLSLDO)
+ (match_operand:DI 1 "register_operand" "r")))))]
"TARGET_TLS && TARGET_ARCH64"
"ldub\t[%1 + %2], %0, %%tldo_add(%3)"
[(set_attr "type" "load")
(define_insn "*tldo_ldsb1_sp64"
[(set (match_operand:HI 0 "register_operand" "=r")
- (sign_extend:HI (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
- (match_operand 3 "tld_symbolic_operand" "")]
- UNSPEC_TLSLDO)
- (match_operand:DI 1 "register_operand" "r")))))]
+ (sign_extend:HI
+ (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+ (match_operand 3 "tld_symbolic_operand" "")]
+ UNSPEC_TLSLDO)
+ (match_operand:DI 1 "register_operand" "r")))))]
"TARGET_TLS && TARGET_ARCH64"
"ldsb\t[%1 + %2], %0, %%tldo_add(%3)"
[(set_attr "type" "sload")
(define_insn "*tldo_ldsb2_sp64"
[(set (match_operand:SI 0 "register_operand" "=r")
- (sign_extend:SI (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
- (match_operand 3 "tld_symbolic_operand" "")]
- UNSPEC_TLSLDO)
- (match_operand:DI 1 "register_operand" "r")))))]
+ (sign_extend:SI
+ (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+ (match_operand 3 "tld_symbolic_operand" "")]
+ UNSPEC_TLSLDO)
+ (match_operand:DI 1 "register_operand" "r")))))]
"TARGET_TLS && TARGET_ARCH64"
"ldsb\t[%1 + %2], %0, %%tldo_add(%3)"
[(set_attr "type" "sload")
(define_insn "*tldo_ldsb3_sp64"
[(set (match_operand:DI 0 "register_operand" "=r")
- (sign_extend:DI (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
- (match_operand 3 "tld_symbolic_operand" "")]
- UNSPEC_TLSLDO)
- (match_operand:DI 1 "register_operand" "r")))))]
+ (sign_extend:DI
+ (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+ (match_operand 3 "tld_symbolic_operand" "")]
+ UNSPEC_TLSLDO)
+ (match_operand:DI 1 "register_operand" "r")))))]
"TARGET_TLS && TARGET_ARCH64"
"ldsb\t[%1 + %2], %0, %%tldo_add(%3)"
[(set_attr "type" "sload")
(define_insn "*tldo_lduh1_sp32"
[(set (match_operand:SI 0 "register_operand" "=r")
- (zero_extend:SI (mem:HI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
- (match_operand 3 "tld_symbolic_operand" "")]
- UNSPEC_TLSLDO)
- (match_operand:SI 1 "register_operand" "r")))))]
+ (zero_extend:SI
+ (mem:HI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
+ (match_operand 3 "tld_symbolic_operand" "")]
+ UNSPEC_TLSLDO)
+ (match_operand:SI 1 "register_operand" "r")))))]
"TARGET_TLS && TARGET_ARCH32"
"lduh\t[%1 + %2], %0, %%tldo_add(%3)"
[(set_attr "type" "load")
(define_insn "*tldo_ldsh1_sp32"
[(set (match_operand:SI 0 "register_operand" "=r")
- (sign_extend:SI (mem:HI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
- (match_operand 3 "tld_symbolic_operand" "")]
- UNSPEC_TLSLDO)
- (match_operand:SI 1 "register_operand" "r")))))]
+ (sign_extend:SI
+ (mem:HI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
+ (match_operand 3 "tld_symbolic_operand" "")]
+ UNSPEC_TLSLDO)
+ (match_operand:SI 1 "register_operand" "r")))))]
"TARGET_TLS && TARGET_ARCH32"
"ldsh\t[%1 + %2], %0, %%tldo_add(%3)"
[(set_attr "type" "sload")
(define_insn "*tldo_lduh1_sp64"
[(set (match_operand:SI 0 "register_operand" "=r")
- (zero_extend:SI (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
- (match_operand 3 "tld_symbolic_operand" "")]
- UNSPEC_TLSLDO)
- (match_operand:DI 1 "register_operand" "r")))))]
+ (zero_extend:SI
+ (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+ (match_operand 3 "tld_symbolic_operand" "")]
+ UNSPEC_TLSLDO)
+ (match_operand:DI 1 "register_operand" "r")))))]
"TARGET_TLS && TARGET_ARCH64"
"lduh\t[%1 + %2], %0, %%tldo_add(%3)"
[(set_attr "type" "load")
(define_insn "*tldo_lduh2_sp64"
[(set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
- (match_operand 3 "tld_symbolic_operand" "")]
- UNSPEC_TLSLDO)
- (match_operand:DI 1 "register_operand" "r")))))]
+ (zero_extend:DI
+ (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+ (match_operand 3 "tld_symbolic_operand" "")]
+ UNSPEC_TLSLDO)
+ (match_operand:DI 1 "register_operand" "r")))))]
"TARGET_TLS && TARGET_ARCH64"
"lduh\t[%1 + %2], %0, %%tldo_add(%3)"
[(set_attr "type" "load")
(define_insn "*tldo_ldsh1_sp64"
[(set (match_operand:SI 0 "register_operand" "=r")
- (sign_extend:SI (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
- (match_operand 3 "tld_symbolic_operand" "")]
- UNSPEC_TLSLDO)
- (match_operand:DI 1 "register_operand" "r")))))]
+ (sign_extend:SI
+ (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+ (match_operand 3 "tld_symbolic_operand" "")]
+ UNSPEC_TLSLDO)
+ (match_operand:DI 1 "register_operand" "r")))))]
"TARGET_TLS && TARGET_ARCH64"
"ldsh\t[%1 + %2], %0, %%tldo_add(%3)"
[(set_attr "type" "sload")
(define_insn "*tldo_ldsh2_sp64"
[(set (match_operand:DI 0 "register_operand" "=r")
- (sign_extend:DI (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
- (match_operand 3 "tld_symbolic_operand" "")]
- UNSPEC_TLSLDO)
- (match_operand:DI 1 "register_operand" "r")))))]
+ (sign_extend:DI
+ (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+ (match_operand 3 "tld_symbolic_operand" "")]
+ UNSPEC_TLSLDO)
+ (match_operand:DI 1 "register_operand" "r")))))]
"TARGET_TLS && TARGET_ARCH64"
"ldsh\t[%1 + %2], %0, %%tldo_add(%3)"
[(set_attr "type" "sload")
(define_insn "*tldo_lduw1_sp64"
[(set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI (mem:SI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
- (match_operand 3 "tld_symbolic_operand" "")]
- UNSPEC_TLSLDO)
- (match_operand:DI 1 "register_operand" "r")))))]
+ (zero_extend:DI
+ (mem:SI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+ (match_operand 3 "tld_symbolic_operand" "")]
+ UNSPEC_TLSLDO)
+ (match_operand:DI 1 "register_operand" "r")))))]
"TARGET_TLS && TARGET_ARCH64"
"lduw\t[%1 + %2], %0, %%tldo_add(%3)"
[(set_attr "type" "load")])
(define_insn "*tldo_ldsw1_sp64"
[(set (match_operand:DI 0 "register_operand" "=r")
- (sign_extend:DI (mem:SI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
- (match_operand 3 "tld_symbolic_operand" "")]
- UNSPEC_TLSLDO)
- (match_operand:DI 1 "register_operand" "r")))))]
+ (sign_extend:DI
+ (mem:SI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+ (match_operand 3 "tld_symbolic_operand" "")]
+ UNSPEC_TLSLDO)
+ (match_operand:DI 1 "register_operand" "r")))))]
"TARGET_TLS && TARGET_ARCH64"
"ldsw\t[%1 + %2], %0, %%tldo_add(%3)"
[(set_attr "type" "sload")
[(set (match_operand:VM64 0 "nonimmediate_operand" "=e,e,e,*r, f,e,m,m,U,T, o,*r")
(match_operand:VM64 1 "input_operand" "Y,C,e, f,*r,m,e,Y,T,U,*r,*r"))]
"TARGET_VIS
- && ! TARGET_ARCH64
+ && TARGET_ARCH32
&& (register_operand (operands[0], <VM64:MODE>mode)
|| register_or_zero_or_all_ones_operand (operands[1], <VM64:MODE>mode))"
"@
(match_operand:VM64 1 "register_operand" ""))]
"reload_completed
&& TARGET_VIS
- && ! TARGET_ARCH64
+ && TARGET_ARCH32
&& (((REGNO (operands[1]) % 2) != 0)
- || ! mem_min_alignment (operands[0], 8))
+ || !mem_min_alignment (operands[0], 8))
&& offsettable_memref_p (operands[0])"
[(clobber (const_int 0))]
{
(match_operand:VM64 1 "register_operand" ""))]
"reload_completed
&& TARGET_VIS
- && ! TARGET_ARCH64
+ && TARGET_ARCH32
&& sparc_split_regreg_legitimate (operands[0], operands[1])"
[(clobber (const_int 0))]
{
DONE;
})
-(define_expand "vec_init<mode>"
+(define_expand "vec_init<VMALL:mode>"
[(match_operand:VMALL 0 "register_operand" "")
(match_operand:VMALL 1 "" "")]
"TARGET_VIS"
(define_mode_iterator VADDSUB [V1SI V2SI V2HI V4HI])
-(define_insn "<plusminus_insn><mode>3"
+(define_insn "<plusminus_insn><VADDSUB:mode>3"
[(set (match_operand:VADDSUB 0 "register_operand" "=<vconstr>")
(plusminus:VADDSUB (match_operand:VADDSUB 1 "register_operand" "<vconstr>")
(match_operand:VADDSUB 2 "register_operand" "<vconstr>")))]
(define_code_attr vlinsn [(ior "or") (and "and") (xor "xor")])
(define_code_attr vlninsn [(ior "nor") (and "nand") (xor "xnor")])
-(define_insn "<code><mode>3"
+(define_insn "*<vlop:code><VL:mode>3"
[(set (match_operand:VL 0 "register_operand" "=<vconstr>")
(vlop:VL (match_operand:VL 1 "register_operand" "<vconstr>")
(match_operand:VL 2 "register_operand" "<vconstr>")))]
(set_attr "fptype" "<vfptype>")
(set_attr "v3pipe" "true")])
-(define_insn "*not_<code><mode>3"
+(define_insn "*not_<vlop:code><VL:mode>3"
[(set (match_operand:VL 0 "register_operand" "=<vconstr>")
(not:VL (vlop:VL (match_operand:VL 1 "register_operand" "<vconstr>")
(match_operand:VL 2 "register_operand" "<vconstr>"))))]
(set_attr "v3pipe" "true")])
;; (ior (not (op1)) (not (op2))) is the canonical form of NAND.
-(define_insn "*nand<mode>_vis"
+(define_insn "*nand<VL:mode>_vis"
[(set (match_operand:VL 0 "register_operand" "=<vconstr>")
(ior:VL (not:VL (match_operand:VL 1 "register_operand" "<vconstr>"))
(not:VL (match_operand:VL 2 "register_operand" "<vconstr>"))))]
(define_code_iterator vlnotop [ior and])
-(define_insn "*<code>_not1<mode>_vis"
+(define_insn "*<vlnotop:code>_not1<VL:mode>_vis"
[(set (match_operand:VL 0 "register_operand" "=<vconstr>")
(vlnotop:VL (not:VL (match_operand:VL 1 "register_operand" "<vconstr>"))
(match_operand:VL 2 "register_operand" "<vconstr>")))]
(set_attr "fptype" "<vfptype>")
(set_attr "v3pipe" "true")])
-(define_insn "*<code>_not2<mode>_vis"
+(define_insn "*<vlnotop:code>_not2<VL:mode>_vis"
[(set (match_operand:VL 0 "register_operand" "=<vconstr>")
(vlnotop:VL (match_operand:VL 1 "register_operand" "<vconstr>")
(not:VL (match_operand:VL 2 "register_operand" "<vconstr>"))))]
(set_attr "fptype" "<vfptype>")
(set_attr "v3pipe" "true")])
-(define_insn "one_cmpl<mode>2"
+(define_insn "one_cmpl<VL:mode>2"
[(set (match_operand:VL 0 "register_operand" "=<vconstr>")
(not:VL (match_operand:VL 1 "register_operand" "<vconstr>")))]
"TARGET_VIS"
[(set (reg:DI GSR_REG) (match_operand:DI 0 "arith_operand" ""))]
"TARGET_VIS"
{
- if (! TARGET_ARCH64)
+ if (TARGET_ARCH32)
{
emit_insn (gen_wrgsr_v8plus (operands[0]));
DONE;
(define_insn "wrgsr_v8plus"
[(set (reg:DI GSR_REG) (match_operand:DI 0 "arith_operand" "I,r"))
(clobber (match_scratch:SI 1 "=X,&h"))]
- "TARGET_VIS && ! TARGET_ARCH64"
+ "TARGET_VIS && TARGET_ARCH32"
{
if (GET_CODE (operands[0]) == CONST_INT
|| sparc_check_64 (operands[0], insn))
[(set (match_operand:DI 0 "register_operand" "") (reg:DI GSR_REG))]
"TARGET_VIS"
{
- if (! TARGET_ARCH64)
+ if (TARGET_ARCH32)
{
emit_insn (gen_rdgsr_v8plus (operands[0]));
DONE;
(define_insn "rdgsr_v8plus"
[(set (match_operand:DI 0 "register_operand" "=r") (reg:DI GSR_REG))
(clobber (match_scratch:SI 1 "=&h"))]
- "TARGET_VIS && ! TARGET_ARCH64"
+ "TARGET_VIS && TARGET_ARCH32"
{
return "rd\t%%gsr, %1\n\tsrlx\t%1, 32, %H0\n\tmov %1, %L0";
}
(define_mode_iterator GCM [V4HI V2SI])
(define_mode_attr gcm_name [(V4HI "16") (V2SI "32")])
-(define_insn "fcmp<code><GCM:gcm_name><P:mode>_vis"
+(define_insn "fcmp<
gcond:code><GCM:gcm_name><P:mode>_vis"
[(set (match_operand:P 0 "register_operand" "=r")
(unspec:P [(gcond:GCM (match_operand:GCM 1 "register_operand" "e")
(match_operand:GCM 2 "register_operand" "e"))]
UNSPEC_FCMP))]
"TARGET_VIS"
- "fcmp<code><GCM:gcm_name>\t%1, %2, %0"
+ "fcmp<gcond:code><GCM:gcm_name>\t%1, %2, %0"
[(set_attr "type" "visl")
(set_attr "fptype" "double")
(set_attr "v3pipe" "true")])
-(define_insn "fpcmp<code>8<P:mode>_vis"
+(define_insn "fpcmp<
gcond:code>8<P:mode>_vis"
[(set (match_operand:P 0 "register_operand" "=r")
(unspec:P [(gcond:V8QI (match_operand:V8QI 1 "register_operand" "e")
(match_operand:V8QI 2 "register_operand" "e"))]
UNSPEC_FCMP))]
"TARGET_VIS4"
- "fpcmp<code>8\t%1, %2, %0"
+ "fpcmp<gcond:code>8\t%1, %2, %0"
[(set_attr "type" "visl")
(set_attr "fptype" "double")])
-(define_expand "vcond<mode><mode>"
+(define_expand "vcond<GCM:mode><GCM:mode>"
[(match_operand:GCM 0 "register_operand" "")
(match_operand:GCM 1 "register_operand" "")
(match_operand:GCM 2 "register_operand" "")
(match_operand:GCM 5 "register_operand" "")])]
"TARGET_VIS3"
{
- sparc_expand_vcond (<MODE>mode, operands,
- UNSPEC_CMASK<gcm_name>,
- UNSPEC_FCMP);
+ sparc_expand_vcond (<MODE>mode, operands, UNSPEC_CMASK<gcm_name>, UNSPEC_FCMP);
DONE;
})
(match_operand:V8QI 5 "register_operand" "")])]
"TARGET_VIS3"
{
- sparc_expand_vcond (V8QImode, operands,
- UNSPEC_CMASK8,
- UNSPEC_FUCMP);
+ sparc_expand_vcond (V8QImode, operands, UNSPEC_CMASK8, UNSPEC_FUCMP);
DONE;
})
;; Unlike constant permutation, we can vastly simplify the compression of
;; the 64-bit selector input to the 32-bit %gsr value by knowing what the
;; width of the input is.
-(define_expand "vec_perm<mode>"
+(define_expand "vec_perm<VM64:mode>"
[(match_operand:VM64 0 "register_operand" "")
(match_operand:VM64 1 "register_operand" "")
(match_operand:VM64 2 "register_operand" "")
"TARGET_VIS2"
{
sparc_expand_vec_perm_bmask (<MODE>mode, operands[3]);
- emit_insn (gen_bshuffle<mode>_vis (operands[0], operands[1], operands[2]));
+ emit_insn (gen_bshuffle<VM64:mode>_vis (operands[0], operands[1], operands[2]));
DONE;
})
(define_code_attr vis3_shift_patname
[(ashift "ashl") (ss_ashift "ssashl") (lshiftrt "lshr") (ashiftrt "ashr")])
-(define_insn "v<vis3_shift_patname><mode>3"
+(define_insn "v<vis3_shift_patname><GCM:mode>3"
[(set (match_operand:GCM 0 "register_operand" "=<vconstr>")
(vis3_shift:GCM (match_operand:GCM 1 "register_operand" "<vconstr>")
(match_operand:GCM 2 "register_operand" "<vconstr>")))]
"<vis3_shift_insn><vbits>\t%1, %2, %0"
[(set_attr "type" "fga")])
-(define_insn "pdistn<mode>_vis"
+(define_insn "pdistn<P:mode>_vis"
[(set (match_operand:P 0 "register_operand" "=r")
(unspec:P [(match_operand:V8QI 1 "register_operand" "e")
(match_operand:V8QI 2 "register_operand" "e")]
(define_code_attr vis3_addsub_ss_patname
[(ss_plus "ssadd") (ss_minus "sssub")])
-(define_insn "<vis3_addsub_ss_patname><mode>3"
+(define_insn "<vis3_addsub_ss_patname><VASS:mode>3"
[(set (match_operand:VASS 0 "register_operand" "=<vconstr>")
(vis3_addsub_ss:VASS (match_operand:VASS 1 "register_operand" "<vconstr>")
(match_operand:VASS 2 "register_operand" "<vconstr>")))]
(define_code_attr vis4_minmax_patname
[(smin "min") (smax "max")])
-(define_insn "<vis4_minmax_patname><mode>3"
+(define_insn "<vis4_minmax_patname><VMMAX:mode>3"
[(set (match_operand:VMMAX 0 "register_operand" "=<vconstr>")
(vis4_minmax:VMMAX (match_operand:VMMAX 1 "register_operand" "<vconstr>")
(match_operand:VMMAX 2 "register_operand" "<vconstr>")))]
(define_code_attr vis4_uminmax_patname
[(umin "minu") (umax "maxu")])
-(define_insn "<vis4_uminmax_patname><mode>3"
+(define_insn "<vis4_uminmax_patname><VMMAX:mode>3"
[(set (match_operand:VMMAX 0 "register_operand" "=<vconstr>")
(vis4_uminmax:VMMAX (match_operand:VMMAX 1 "register_operand" "<vconstr>")
(match_operand:VMMAX 2 "register_operand" "<vconstr>")))]
(define_code_attr vis4_addsub_us_patname
[(us_plus "usadd") (us_minus "ussub")])
-(define_insn "<vis4_addsub_us_patname><mode>3"
+(define_insn "<vis4_addsub_us_patname><VAUS:mode>3"
[(set (match_operand:VAUS 0 "register_operand" "=<vconstr>")
(vis4_addsub_us:VAUS (match_operand:VAUS 1 "register_operand" "<vconstr>")
(match_operand:VAUS 2 "register_operand" "<vconstr>")))]
"<vis4_addsub_us_insn><vbits>\t%1, %2, %0"
[(set_attr "type" "fga")])
-(define_insn "fucmp<code>8<P:mode>_vis"
+(define_insn "fucmp<
gcond:code>8<P:mode>_vis"
[(set (match_operand:P 0 "register_operand" "=r")
- (unspec:P [(gcond:V8QI (match_operand:V8QI 1 "register_operand" "e")
+ (unspec:P [(gcond:V8QI (match_operand:V8QI 1 "register_operand" "e")
(match_operand:V8QI 2 "register_operand" "e"))]
UNSPEC_FUCMP))]
"TARGET_VIS3"
- "fucmp<code>8\t%1, %2, %0"
+ "fucmp<gcond:code>8\t%1, %2, %0"
[(set_attr "type" "visl")
(set_attr "v3pipe" "true")])
-(define_insn "fpcmpu<code><GCM:gcm_name><P:mode>_vis"
+(define_insn "fpcmpu<
gcond:code><GCM:gcm_name><P:mode>_vis"
[(set (match_operand:P 0 "register_operand" "=r")
- (unspec:P [(gcond:GCM (match_operand:GCM 1 "register_operand" "e")
+ (unspec:P [(gcond:GCM (match_operand:GCM 1 "register_operand" "e")
(match_operand:GCM 2 "register_operand" "e"))]
UNSPEC_FUCMP))]
"TARGET_VIS4"
- "fpcmpu<code><GCM:gcm_name>\t%1, %2, %0"
+ "fpcmpu<gcond:code><GCM:gcm_name>\t%1, %2, %0"
[(set_attr "type" "visl")
(set_attr "fptype" "double")])
projects / platform / upstream / gcc.git / commitdiff