struct fsi_priv {
void __iomem *base;
+ phys_addr_t phys;
struct fsi_master *master;
struct fsi_stream playback;
struct dma_slave_config cfg = {};
int ret;
- cfg.dst_addr = 0; /* use default addr */
- cfg.src_addr = 0; /* use default addr */
- cfg.direction = is_play ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
+ if (is_play) {
+ cfg.dst_addr = fsi->phys + REG_DODT;
+ cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+ cfg.direction = DMA_MEM_TO_DEV;
+ } else {
+ cfg.src_addr = fsi->phys + REG_DIDT;
+ cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+ cfg.direction = DMA_DEV_TO_MEM;
+ }
ret = dmaengine_slave_config(io->chan, &cfg);
if (ret < 0) {
/* FSI A setting */
fsi = &master->fsia;
fsi->base = master->base;
+ fsi->phys = res->start;
fsi->master = master;
fsi_port_info_init(fsi, &info.port_a);
fsi_handler_init(fsi, &info.port_a);
/* FSI B setting */
fsi = &master->fsib;
fsi->base = master->base + 0x40;
+ fsi->phys = res->start + 0x40;
fsi->master = master;
fsi_port_info_init(fsi, &info.port_b);
fsi_handler_init(fsi, &info.port_b);