* i386.md (QImode patterns): Remove '*' before the 'r' constraints.
* i386.h (procesor_costs): Add movzbl_load field.
(HARD_REGNO_MODE_OK): Accept QImode on non PARTIAL_REGISTER_STALL in
non-Q registers, accept DImode registers anywhere.
(Q_CLASS_P): New.
(MEMORY_MOVE_COST): Calculate QImode moves correctly.
* i386.c (*_cost): Set value for movxbl_load field.
From-SVN: r30746
Fri Nov 26 10:59:12 CET 1999 Jan Hubicka <hubicka@freesoft.cz>
+ * i386.md (QImode patterns): Remove '*' before the 'r' constraints.
+ * i386.h (procesor_costs): Add movzbl_load field.
+ (HARD_REGNO_MODE_OK): Accept QImode on non PARTIAL_REGISTER_STALL in
+ non-Q registers, accept DImode registers anywhere.
+ (Q_CLASS_P): New.
+ (MEMORY_MOVE_COST): Calculate QImode moves correctly.
+ * i386.c (*_cost): Set value for movxbl_load field.
+
* (addsi): New add to lea splitter.
(ashlsi): Likewise.
(lea to add/shift peep2): New.
1, /* cost of multiply per each bit set */
23, /* cost of a divide/mod */
15, /* "large" insn */
+ 4, /* cost for loading QImode using movzbl */
{2, 4, 2}, /* cost of loading integer registers
in QImode, HImode and SImode.
Relative to reg-reg move (2). */
1, /* cost of multiply per each bit set */
40, /* cost of a divide/mod */
15, /* "large" insn */
+ 4, /* cost for loading QImode using movzbl */
{2, 4, 2}, /* cost of loading integer registers
in QImode, HImode and SImode.
Relative to reg-reg move (2). */
0, /* cost of multiply per each bit set */
25, /* cost of a divide/mod */
8, /* "large" insn */
+ 6, /* cost for loading QImode using movzbl */
{2, 4, 2}, /* cost of loading integer registers
in QImode, HImode and SImode.
Relative to reg-reg move (2). */
0, /* cost of multiply per each bit set */
17, /* cost of a divide/mod */
8, /* "large" insn */
+ 2, /* cost for loading QImode using movzbl */
{4, 4, 4}, /* cost of loading integer registers
in QImode, HImode and SImode.
Relative to reg-reg move (2). */
0, /* cost of multiply per each bit set */
18, /* cost of a divide/mod */
8, /* "large" insn */
+ 3, /* cost for loading QImode using movzbl */
{4, 5, 4}, /* cost of loading integer registers
in QImode, HImode and SImode.
Relative to reg-reg move (2). */
int mult_bit; /* cost of multiply per each bit set */
int divide; /* cost of a divide/mod */
int large_insn; /* insns larger than this cost more */
+ int movzbl_load; /* cost of loading using movzbl */
int int_load[3]; /* cost of loading integer registers
in QImode, HImode and SImode relative
to reg-reg move (2). */
? ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
&& GET_MODE_UNIT_SIZE (MODE) <= (LONG_DOUBLE_TYPE_SIZE == 96 ? 12 : 8))\
- /* Only allow DImode in even registers. */ \
- : (MODE) == DImode && ((REGNO) & 1) ? 0 \
- /* The first four integer regs can hold any mode. */ \
: (REGNO) < 4 ? 1 \
/* Other regs cannot do byte accesses. */ \
: (MODE) != QImode ? 1 \
- : reload_in_progress || reload_completed)
+ : reload_in_progress || reload_completed \
+ || !TARGET_PARTIAL_REG_STALL)
/* Value is 1 if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.
#define FLOAT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, FLOAT_REGS))
+#define Q_CLASS_P(CLASS) (reg_class_subset_p (CLASS, Q_REGS))
+
/* Give names of register classes as strings for dump file. */
#define REG_CLASS_NAMES \
If moving between registers and memory is more expensive than
between two registers, you should define this macro to express the
- relative cost. */
+ relative cost.
+
+ Model also increased moving costs of QImode registers in non
+ Q_REGS classes.
+ */
#define MEMORY_MOVE_COST(MODE,CLASS,IN) \
(FLOAT_CLASS_P (CLASS) \
? (IN ? ix86_cost->fp_load[1] : ix86_cost->fp_store[1]) \
: (IN ? ix86_cost->fp_load[2] : ix86_cost->fp_store[2]))) \
: (GET_MODE_SIZE (MODE)==1 \
- ? (IN ? ix86_cost->int_load[0] : ix86_cost->int_store[0]) \
+ ? (IN ? (Q_CLASS_P (CLASS) ? ix86_cost->int_load[0] \
+ : ix86_cost->movzbl_load) \
+ : (Q_CLASS_P (CLASS) ? ix86_cost->int_store[0] \
+ : ix86_cost->int_store[0] + 4)) \
: (GET_MODE_SIZE (MODE)==2 \
? (IN ? ix86_cost->int_load[1] : ix86_cost->int_store[1]) \
: ((IN ? ix86_cost->int_load[2] : ix86_cost->int_store[2]) \
(set_attr "length_prefix" "1")])
(define_insn "*movqi_1"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q,*r,*r,m")
- (match_operand:QI 1 "general_operand" "qn,qm,*rn,qm,qn"))]
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q,r,?r,m")
+ (match_operand:QI 1 "general_operand" "qn,qm,rn,qm,qn"))]
"GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
"*
{
[(set_attr "type" "imovx")])
(define_insn "*movqi_extv_1"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=qm*r")
- (sign_extract:QI (match_operand:SI 1 "register_operand" "q")
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,?r")
+ (sign_extract:QI (match_operand:SI 1 "register_operand" "q,q")
(const_int 8)
(const_int 8)))]
""
[(set_attr "type" "imovx")])
(define_insn "*movqi_extzv_1"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=qm*r")
- (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "q")
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,?r")
+ (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "q,q")
(const_int 8)
(const_int 8)) 0))]
""
;; %%% Potential partial reg stall on alternative 2. What to do?
(define_insn "*addqi_1"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,*r")
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
(plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:QI 2 "general_operand" "qn,qmn,*rn")))
+ (match_operand:QI 2 "general_operand" "qn,qmn,rn")))
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (PLUS, QImode, operands)"
"*
;; %%% Potential partial reg stall on alternative 2. What to do?
(define_insn "*andqi_1"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,*r")
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
(and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:QI 2 "general_operand" "qi,qmi,*ri")))
+ (match_operand:QI 2 "general_operand" "qi,qmi,ri")))
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (AND, QImode, operands)"
"@
;; %%% Potential partial reg stall on alternative 2. What to do?
(define_insn "*iorqi_1"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,*r")
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
(ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:QI 2 "general_operand" "qmi,qi,*ri")))
+ (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (IOR, QImode, operands)"
"@
;; %%% Potential partial reg stall on alternative 2. What to do?
(define_insn "*xorqi_1"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,*r")
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
(xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:QI 2 "general_operand" "qmi,qi,*ri")))
+ (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
(clobber (reg:CC 17))]
"ix86_binary_operator_ok (XOR, QImode, operands)"
"@
"ix86_expand_unary_operator (NOT, QImode, operands); DONE;")
(define_insn "*one_cmplqi2_1"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,*r")
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
(not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
"ix86_unary_operator_ok (NEG, QImode, operands)"
"@