intel: Align untiled buffer pitch to 64B.

This is the largest untiled pitch requirement from gen2 through gen4.
It's only the case for gen3 rendering to color regions with depth, but
it's rare for this to be a significant factor in memory usage -- for
example, gen4 requires 1 or 2 times the element size, or up to 64
bytes depending on the size of the elements.  This is easier than
encoding all the various little quirks for untiled pitch alignment,
since we rarely do untiled now.

diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index c3b5d6a..8e46e37 100644 (file)
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -257,8 +257,11 @@ drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
        unsigned long tile_width;
        unsigned long i;
 
+       /* If untiled, then just align it so that we can do rendering
+        * to it with the 3D engine.
+        */
        if (tiling_mode == I915_TILING_NONE)
-               return pitch;
+               return ALIGN(pitch, 64);
 
        if (tiling_mode == I915_TILING_X)
                tile_width = 512;