drm/amd/display: Clean up warnings in amdgpu_dm_pp_smu.c

Fixes the following category of checkpatch warning:

WARNING: Block comments use a trailing */ on a separate line
+                                * non-boosted one. */

WARNING: suspect code indent for conditional statements (8, 24)
+       if ((adev->asic_type >= CHIP_POLARIS10) &&
[...]
+                       return true;

Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index 75284e2..848c5b4 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -334,7 +334,8 @@ bool dm_pp_get_clock_levels_by_type(
                        if (dc_clks->clocks_in_khz[i] > validation_clks.engine_max_clock) {
                                /* This clock is higher the validation clock.
                                 * Than means the previous one is the highest
-                                * non-boosted one. */
+                                * non-boosted one.
+                                */
                                DRM_INFO("DM_PPLIB: reducing engine clock level from %d to %d\n",
                                                dc_clks->num_levels, i);
                                dc_clks->num_levels = i > 0 ? i : 1;
@@ -406,10 +407,10 @@ bool dm_pp_notify_wm_clock_changes(
         * TODO: expand this to other ASICs
         */
        if ((adev->asic_type >= CHIP_POLARIS10) &&
-            (adev->asic_type <= CHIP_VEGAM) &&
-            !amdgpu_dpm_set_watermarks_for_clocks_ranges(adev,
-                                               (void *)wm_with_clock_ranges))
-                       return true;
+           (adev->asic_type <= CHIP_VEGAM) &&
+           !amdgpu_dpm_set_watermarks_for_clocks_ranges(adev,
+                                                        (void *)wm_with_clock_ranges))
+               return true;
 
        return false;
 }