mpc8308: support for Freescale MPC8308 cpu

This patch adds basic support for Freescale MPC8308 CPU. Serial ports,
NOR flash and integrated Ethernet controllers are supported.
PCI Express is also supported. eSDHC, NAND and USB may work but aren't
tested (using ULPI PHY requires additional patch).

Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c
index b664c64..42387b4 100644 (file)
--- a/arch/powerpc/cpu/mpc83xx/cpu.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu.c
@@ -55,6 +55,7 @@ int checkcpu(void)
                char name[15];
                u32 partid;
        } cpu_type_list [] = {
+               CPU_TYPE_ENTRY(8308),
                CPU_TYPE_ENTRY(8311),
                CPU_TYPE_ENTRY(8313),
                CPU_TYPE_ENTRY(8314),

diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index b5076a9..d04b192 100644 (file)
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -100,7 +100,8 @@ int get_clocks(void)
        u32 lcrr;
 
        u32 csb_clk;
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+       defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
        u32 tsec1_clk;
        u32 tsec2_clk;
        u32 usbdr_clk;
@@ -132,7 +133,8 @@ int get_clocks(void)
        u32 qe_clk;
        u32 brg_clk;
 #endif
-#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC831x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+       defined(CONFIG_MPC837x)
        u32 pciexp1_clk;
        u32 pciexp2_clk;
 #endif
@@ -164,7 +166,8 @@ int get_clocks(void)
 
        sccr = im->clk.sccr;
 
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+       defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
        switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
        case 0:
                tsec1_clk = 0;
@@ -202,7 +205,8 @@ int get_clocks(void)
        }
 #endif
 
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) || \
+       defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
        switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
        case 0:
                tsec2_clk = 0;
@@ -319,7 +323,7 @@ int get_clocks(void)
        i2c1_clk = csb_clk;
 #elif defined(CONFIG_MPC832x)
        i2c1_clk = enc_clk;
-#elif defined(CONFIG_MPC831x)
+#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
        i2c1_clk = enc_clk;
 #elif defined(CONFIG_FSL_ESDHC)
        i2c1_clk = sdhc_clk;
@@ -328,7 +332,8 @@ int get_clocks(void)
        i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
 #endif
 
-#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC831x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+       defined(CONFIG_MPC837x)
        switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
        case 0:
                pciexp1_clk = 0;
@@ -444,7 +449,8 @@ int get_clocks(void)
 #endif
 
        gd->csb_clk = csb_clk;
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+       defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
        gd->tsec1_clk = tsec1_clk;
        gd->tsec2_clk = tsec2_clk;
        gd->usbdr_clk = usbdr_clk;
@@ -525,7 +531,8 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 #if defined(CONFIG_FSL_ESDHC)
        printf("  SDHC:                %-4s MHz\n", strmhz(buf, gd->sdhc_clk));
 #endif
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+       defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
        printf("  TSEC1:               %-4s MHz\n", strmhz(buf, gd->tsec1_clk));
        printf("  TSEC2:               %-4s MHz\n", strmhz(buf, gd->tsec2_clk));
        printf("  USB DR:              %-4s MHz\n", strmhz(buf, gd->usbdr_clk));

diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index d3dd44e..c854ce9 100644 (file)
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -60,7 +60,8 @@ typedef       struct  global_data {
 #if defined(CONFIG_MPC83xx)
        /* There are other clocks in the MPC83XX */
        u32 csb_clk;
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+       defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
        u32 tsec1_clk;
        u32 tsec2_clk;
        u32 usbdr_clk;
@@ -76,7 +77,8 @@ typedef       struct  global_data {
        u32 lbiu_clk;
        u32 lclk_clk;
        u32 pci_clk;
-#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC831x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+       defined(CONFIG_MPC837x)
        u32 pciexp1_clk;
        u32 pciexp2_clk;
 #endif

diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index 6b42a73..3a9cdc4 100644 (file)
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -73,7 +73,11 @@ typedef struct sysconf83xx {
        u32 obir;               /* Output Buffer Impedance Register */
        u8 res8[0xC];
        u32 pecr1;              /* PCI Express control register 1 */
+#ifdef CONFIG_MPC8308
+       u32 sdhccr;             /* eSDHC Control Registers for MPC8308 */
+#else
        u32 pecr2;              /* PCI Express control register 2 */
+#endif
        u8 res9[0xB8];
 } sysconf83xx_t;
 
@@ -589,7 +593,14 @@ typedef struct sdhc83xx {
  * SerDes
  */
 typedef struct serdes83xx {
-       u8 fixme[0x100];
+       u32 srdscr0;
+       u32 srdscr1;
+       u32 srdscr2;
+       u32 srdscr3;
+       u32 srdscr4;
+       u8 res0[0xc];
+       u32 srdsrstctl;
+       u8 res1[0xdc];
 } serdes83xx_t;
 
 /*
@@ -691,7 +702,7 @@ typedef struct immap {
        u8                      res7[0xC0000];
 } immap_t;
 
-#elif defined(CONFIG_MPC8315)
+#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
 typedef struct immap {
        sysconf83xx_t           sysconf;        /* System configuration */
        wdt83xx_t               wdt;            /* Watch Dog Timer (WDT) Registers */

diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h
index 41737d3..b0082af 100644 (file)
--- a/arch/powerpc/include/asm/mpc8xxx_spi.h
+++ b/arch/powerpc/include/asm/mpc8xxx_spi.h
@@ -27,9 +27,10 @@
 
 #include <asm/types.h>
 
-#if defined(CONFIG_MPC834x) || \
+#if defined(CONFIG_MPC8308) || \
        defined(CONFIG_MPC8313) || \
        defined(CONFIG_MPC8315) || \
+       defined(CONFIG_MPC834x) || \
        defined(CONFIG_MPC837x)
 
 typedef struct spi8xxx {

diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 5214911..ba6cdf1 100644 (file)
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2010 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -65,6 +65,7 @@
 #define PARTID_NO_E(spridr)            ((spridr & 0xFFFE0000) >> 16)
 #define SPR_FAMILY(spridr)             ((spridr & 0xFFF00000) >> 20)
 
+#define SPR_8308                       0x8100
 #define SPR_831X_FAMILY                        0x80B
 #define SPR_8311                       0x80B2
 #define SPR_8313                       0x80B0
@@ -115,8 +116,9 @@
 #define SPCR_TSEC2EP                   0x00000003      /* TSEC2 emergency priority */
 #define SPCR_TSEC2EP_SHIFT             (31-31)
 
-#elif defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
-/* SPCR bits - MPC831x and MPC837x specific */
+#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+       defined(CONFIG_MPC837x)
+/* SPCR bits - MPC8308, MPC831x and MPC837x specific */
 #define SPCR_TSECDP                    0x00003000      /* TSEC data priority */
 #define SPCR_TSECDP_SHIFT              (31-19)
 #define SPCR_TSECBDP                   0x00000C00      /* TSEC buffer descriptor priority */
@@ -473,7 +475,7 @@
 #define HRCWL_CE_TO_PLL_1X30           0x0000001E
 #define HRCWL_CE_TO_PLL_1X31           0x0000001F
 
-#elif defined(CONFIG_MPC8315)
+#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
 #define HRCWL_SVCOD                    0x30000000
 #define HRCWL_SVCOD_SHIFT              28
 #define HRCWL_SVCOD_DIV_2              0x00000000
@@ -541,7 +543,8 @@
 #define HRCWH_ROM_LOC_LOCAL_16BIT      0x00600000
 #define HRCWH_ROM_LOC_LOCAL_32BIT      0x00700000
 
-#if defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+       defined(CONFIG_MPC837x)
 #define HRCWH_ROM_LOC_NAND_SP_8BIT     0x00100000
 #define HRCWH_ROM_LOC_NAND_SP_16BIT    0x00200000
 #define HRCWH_ROM_LOC_NAND_LP_8BIT     0x00500000
@@ -592,7 +595,8 @@
 
 /* RSR - Reset Status Register
  */
-#if defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+       defined(CONFIG_MPC837x)
 #define RSR_RSTSRC                     0xF0000000      /* Reset source */
 #define RSR_RSTSRC_SHIFT               28
 #else
@@ -734,8 +738,8 @@
 #define SCCR_USBDRCM_2                 0x00200000
 #define SCCR_USBDRCM_3                 0x00300000
 
-#elif defined(CONFIG_MPC8315)
-/* SCCR bits - MPC8315 specific */
+#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
+/* SCCR bits - MPC8315/MPC8308 specific */
 #define SCCR_TSEC1CM                   0xc0000000
 #define SCCR_TSEC1CM_SHIFT             30
 #define SCCR_TSEC1CM_0                 0x00000000
@@ -750,6 +754,13 @@
 #define SCCR_TSEC2CM_2                 0x20000000
 #define SCCR_TSEC2CM_3                 0x30000000
 
+#define SCCR_SDHCCM                    0x0c000000
+#define SCCR_SDHCCM_SHIFT              26
+#define SCCR_SDHCCM_0                  0x00000000
+#define SCCR_SDHCCM_1                  0x04000000
+#define SCCR_SDHCCM_2                  0x08000000
+#define SCCR_SDHCCM_3                  0x0c000000
+
 #define SCCR_USBDRCM                   0x00c00000
 #define SCCR_USBDRCM_SHIFT             22
 #define SCCR_USBDRCM_0                 0x00000000