net/mlx5e: E-Switch, Add PTP counters for uplink representor
authorAya Levin <ayal@nvidia.com>
Wed, 19 Jan 2022 16:28:20 +0000 (18:28 +0200)
committerSaeed Mahameed <saeedm@nvidia.com>
Thu, 17 Feb 2022 07:55:14 +0000 (23:55 -0800)
There is a configuration where the uplink interface is the synchronizer.
Add PTP counters for this interface for monitoring.

Signed-off-by: Aya Levin <ayal@nvidia.com>
Reviewed-by: Tariq Toukan <tariqt@nvidia.com>
Reviewed-by: Maor Dickman <maord@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
drivers/net/ethernet/mellanox/mlx5/core/en_rep.c
drivers/net/ethernet/mellanox/mlx5/core/en_stats.c
drivers/net/ethernet/mellanox/mlx5/core/en_stats.h

index a3f257623af4337ce94f03793d333b3d2ab4864e..4459e55850754983d23bf21b30311bab1a38cb07 100644 (file)
@@ -1094,6 +1094,7 @@ static mlx5e_stats_grp_t mlx5e_ul_rep_stats_grps[] = {
        &MLX5E_STATS_GRP(ipsec_sw),
        &MLX5E_STATS_GRP(ipsec_hw),
 #endif
+       &MLX5E_STATS_GRP(ptp),
 };
 
 static unsigned int mlx5e_ul_rep_stats_grps_num(struct mlx5e_priv *priv)
index 26e326fe503ceaba24bfbc75f0b5ee41da4b01cd..3e5d8c788026aeba982b4921120244927ee5a58b 100644 (file)
@@ -2348,7 +2348,7 @@ MLX5E_DEFINE_STATS_GRP(channels, 0);
 MLX5E_DEFINE_STATS_GRP(per_port_buff_congest, 0);
 MLX5E_DEFINE_STATS_GRP(eth_ext, 0);
 static MLX5E_DEFINE_STATS_GRP(tls, 0);
-static MLX5E_DEFINE_STATS_GRP(ptp, 0);
+MLX5E_DEFINE_STATS_GRP(ptp, 0);
 static MLX5E_DEFINE_STATS_GRP(qos, 0);
 
 /* The stats groups order is opposite to the update_stats() order calls */
index 2c1ed5b81be676e0507b504564bf961131b37eae..14eaf923e7b3ed4d817d63e5c6bbf44c622bfa93 100644 (file)
@@ -459,5 +459,6 @@ extern MLX5E_DECLARE_STATS_GRP(channels);
 extern MLX5E_DECLARE_STATS_GRP(per_port_buff_congest);
 extern MLX5E_DECLARE_STATS_GRP(ipsec_hw);
 extern MLX5E_DECLARE_STATS_GRP(ipsec_sw);
+extern MLX5E_DECLARE_STATS_GRP(ptp);
 
 #endif /* __MLX5_EN_STATS_H__ */