clk: renesas: rzg2l: Add support to handle MUX clocks

Add support to handle mux clocks in order to select a clock source
from multiple sources.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210922155145.28156-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 761922e..69eba5a 100644 (file)
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -130,6 +130,26 @@ rzg2l_cpg_div_clk_register(const struct cpg_core_clk *core,
        return clk_hw->clk;
 }
 
+static struct clk * __init
+rzg2l_cpg_mux_clk_register(const struct cpg_core_clk *core,
+                          void __iomem *base,
+                          struct rzg2l_cpg_priv *priv)
+{
+       const struct clk_hw *clk_hw;
+
+       clk_hw = devm_clk_hw_register_mux(priv->dev, core->name,
+                                         core->parent_names, core->num_parents,
+                                         core->flag,
+                                         base + GET_REG_OFFSET(core->conf),
+                                         GET_SHIFT(core->conf),
+                                         GET_WIDTH(core->conf),
+                                         core->mux_flags, &priv->rmw_lock);
+       if (IS_ERR(clk_hw))
+               return ERR_CAST(clk_hw);
+
+       return clk_hw->clk;
+}
+
 struct pll_clk {
        struct clk_hw hw;
        unsigned int conf;
@@ -288,6 +308,9 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core,
                clk = rzg2l_cpg_div_clk_register(core, priv->clks,
                                                 priv->base, priv);
                break;
+       case CLK_TYPE_MUX:
+               clk = rzg2l_cpg_mux_clk_register(core, priv->base, priv);
+               break;
        default:
                goto fail;
        }

diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index 6369528..f538ffa 100644 (file)
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -24,6 +24,9 @@
 #define DIVPL3A                DDIV_PACK(CPG_PL3A_DDIV, 0, 3)
 #define DIVPL3B                DDIV_PACK(CPG_PL3A_DDIV, 4, 3)
 
+#define SEL_PLL_PACK(offset, bitpos, size) \
+               (((offset) << 20) | ((bitpos) << 12) | ((size) << 8))
+
 /**
  * Definitions of CPG Core Clocks
  *
@@ -43,6 +46,7 @@ struct cpg_core_clk {
        const struct clk_div_table *dtable;
        const char * const *parent_names;
        int flag;
+       int mux_flags;
        int num_parents;
 };
 
@@ -54,6 +58,9 @@ enum clk_types {
 
        /* Clock with divider */
        CLK_TYPE_DIV,
+
+       /* Clock with clock source selector */
+       CLK_TYPE_MUX,
 };
 
 #define DEF_TYPE(_name, _id, _type...) \
@@ -69,6 +76,11 @@ enum clk_types {
 #define DEF_DIV(_name, _id, _parent, _conf, _dtable, _flag) \
        DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \
                 .parent = _parent, .dtable = _dtable, .flag = _flag)
+#define DEF_MUX(_name, _id, _conf, _parent_names, _num_parents, _flag, \
+               _mux_flags) \
+       DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
+                .parent_names = _parent_names, .num_parents = _num_parents, \
+                .flag = _flag, .mux_flags = _mux_flags)
 
 /**
  * struct rzg2l_mod_clk - Module Clocks definitions