drm/amd/display: Add DCN3 chip ids
authorBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Thu, 21 May 2020 16:28:39 +0000 (12:28 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 1 Jul 2020 05:59:14 +0000 (01:59 -0400)
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/include/dal_asic_id.h
drivers/gpu/drm/amd/display/include/dal_types.h

index 2359e88..abeb58d 100644 (file)
@@ -166,6 +166,7 @@ enum {
        NV_NAVI10_P_A0      = 1,
        NV_NAVI12_P_A0      = 10,
        NV_NAVI14_M_A0      = 20,
+       NV_SIENNA_CICHLID_P_A0      = 40,
        NV_UNKNOWN          = 0xFF
 };
 
@@ -173,6 +174,9 @@ enum {
 #define ASICREV_IS_NAVI12_P(eChipRev)        ((eChipRev >= NV_NAVI12_P_A0) && (eChipRev < NV_NAVI14_M_A0))
 #define ASICREV_IS_NAVI14_M(eChipRev)        ((eChipRev >= NV_NAVI14_M_A0) && (eChipRev < NV_UNKNOWN))
 #define ASICREV_IS_RENOIR(eChipRev) ((eChipRev >= RENOIR_A0) && (eChipRev < RAVEN1_F0))
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#define ASICREV_IS_SIENNA_CICHLID_P(eChipRev)        ((eChipRev >= NV_SIENNA_CICHLID_P_A0))
+#endif
 
 /*
  * ASIC chip ID
index 0b68591..b67c9fa 100644 (file)
@@ -48,6 +48,7 @@ enum dce_version {
        DCN_VERSION_1_01,
        DCN_VERSION_2_0,
        DCN_VERSION_2_1,
+       DCN_VERSION_3_0,
        DCN_VERSION_MAX
 };