/*config extern phy*/
if (internal_phy == 0) {
+ if (of_property_read_u32(np, "tx_delay", &external_tx_delay))
+ pr_debug("set exphy tx delay\n");
+ if (of_property_read_u32(np, "rx_delay", &external_rx_delay))
+ pr_debug("set exphy rx delay\n");
/* only exphy support wol since g12a*/
/*we enable/disable wol with item in dts with "wol=<1>"*/
if (of_property_read_u32(np, "wol",
#ifdef CONFIG_AMLOGIC_ETH_PRIVE
int stmmac_pltfr_suspend(struct device *dev);
int stmmac_pltfr_resume(struct device *dev);
+extern unsigned int external_rx_delay;
+extern unsigned int external_tx_delay;
#endif
extern const struct dev_pm_ops stmmac_pltfr_pm_ops;
return priv->plat->bsp_priv;
}
-
#endif /* __STMMAC_PLATFORM_H__ */
#ifdef CONFIG_AMLOGIC_ETH_PRIVE
unsigned int support_external_phy_wol;
+unsigned int external_rx_delay;
+unsigned int external_tx_delay;
#endif
static int rtl821x_ack_interrupt(struct phy_device *phydev)
{
phy_write(phydev, 0x11, reg);
#ifdef CONFIG_AMLOGIC_ETH_PRIVE
+ if (external_rx_delay) {
+ /*add 2ns delay for rx*/
+ phy_write(phydev, RTL8211F_PAGE_SELECT, 0xd08);
+ reg = phy_read(phydev, 0x15);
+ reg = phy_write(phydev, 0x15, reg | 0x8);
+ phy_write(phydev, RTL8211F_PAGE_SELECT, 0x0);
+ }
+ if (external_tx_delay) {
+ /*add 2ns delay for tx*/
+ phy_write(phydev, RTL8211F_PAGE_SELECT, 0xd08);
+ reg = phy_read(phydev, 0x11);
+ reg = phy_write(phydev, 0x11, reg | 0x100);
+ phy_write(phydev, RTL8211F_PAGE_SELECT, 0x0);
+ }
/*disable clk_out pin 35 set page 0x0a43 reg25.0 as 0*/
phy_write(phydev, RTL8211F_PAGE_SELECT, 0x0a43);
reg = phy_read(phydev, 0x19);