* config/i386/sync.md (memory_barrier_nosse): Disable also for

	TARGET_64BIT.  Remove special asm template for TARGET_64BIT case.
	(memory_barrier): Do not generate memory_barrier_nosse instruction
	for TARGET_64BIT.
	* config/i386/sse.md (*sse2_mfence): Also enable for TARGET_64BIT.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@142224 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9238560..8efb64a 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2008-11-26  Uros Bizjak  <ubizjak@gmail.com>
+
+       * config/i386/sync.md (memory_barrier_nosse): Disable also for
+       TARGET_64BIT.  Remove special asm template for TARGET_64BIT case.
+       (memory_barrier): Do not generate memory_barrier_nosse instruction
+       for TARGET_64BIT.
+       * config/i386/sse.md (*sse2_mfence): Also enable for TARGET_64BIT.
+
 2008-11-26  Fredrik Unger  <fred@tree.se>
 
        * config/soft-fp/floatuntisf.c (__floatuntisf): Correct
@@ -78,7 +86,7 @@
 2008-11-25  Uros Bizjak  <ubizjak@gmail.com>
 
        PR target/38254
-       * config/i386/sync.md (memory_barrier_nosse): New insn
+       * config/i386/sync.md (memory_barrier_nosse): New insn pattern.
        (memory_barrier): Generate memory_barrier_nosse insn for !TARGET_SSE2.
 
 2008-11-24  Maxim Kuvyrkov  <maxim@codesourcery.com>

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 48c9f6d..997edc5 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -7719,7 +7719,7 @@
 (define_insn "*sse2_mfence"
   [(set (match_operand:BLK 0 "" "")
        (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
-  "TARGET_SSE2"
+  "TARGET_64BIT || TARGET_SSE2"
   "mfence"
   [(set_attr "type" "sse")
    (set_attr "memory" "unknown")])

diff --git a/gcc/config/i386/sync.md b/gcc/config/i386/sync.md
index 8aad0c4..4b36d45 100644 (file)
--- a/gcc/config/i386/sync.md
+++ b/gcc/config/i386/sync.md
@@ -39,7 +39,7 @@
   operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
   MEM_VOLATILE_P (operands[0]) = 1;
 
-  if (!TARGET_SSE2)
+  if (!(TARGET_64BIT || TARGET_SSE2))
     {
       emit_insn (gen_memory_barrier_nosse (operands[0]));
       DONE;
@@ -50,14 +50,8 @@
   [(set (match_operand:BLK 0 "" "")
        (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))
    (clobber (reg:CC FLAGS_REG))]
-
-  "!TARGET_SSE2"
-{
-  if (TARGET_64BIT)
-    return "lock{%;| }or{q}\t{$0, (%%rsp)|QWORD PTR [rsp], 0}";
-  else
-    return "lock{%;| }or{l}\t{$0, (%%esp)|DWORD PTR [esp], 0}";
-}
+  "!(TARGET_64BIT || TARGET_SSE2)"
+  "lock{%;| }or{l}\t{$0, (%%esp)|DWORD PTR [esp], 0}"
   [(set_attr "memory" "unknown")])
 
 ;; ??? It would be possible to use cmpxchg8b on pentium for DImode