[SVE] Fix some logical arithmetic tests

There were some right-shift tests in

  CodeGen/AArch64/sve-int-arith-imm.ll

that were being folded away because we were shifting all the bits
out to the right. I've updated the tests to ensure this doesn't
happen.

diff --git a/llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll b/llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll
index ad909c0..9cf22a3 100644 (file)
--- a/llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll
+++ b/llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
 ; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
 
@@ -8,9 +9,10 @@
 ; SMAX
 ;
 define <vscale x 16 x i8> @smax_i8_pos(<vscale x 16 x i8> %a) {
-; CHECK-LABEL: smax_i8_pos
-; CHECK: smax z0.b, z0.b, #27
-; CHECK-NEXT: ret
+; CHECK-LABEL: smax_i8_pos:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    smax z0.b, z0.b, #27
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 16 x i8> undef, i8 27, i32 0
   %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %cmp = icmp sgt <vscale x 16 x i8> %a, %splat
@@ -19,9 +21,10 @@ define <vscale x 16 x i8> @smax_i8_pos(<vscale x 16 x i8> %a) {
 }
 
 define <vscale x 16 x i8> @smax_i8_neg(<vscale x 16 x i8> %a) {
-; CHECK-LABEL: smax_i8_neg
-; CHECK: smax z0.b, z0.b, #-58
-; CHECK-NEXT: ret
+; CHECK-LABEL: smax_i8_neg:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    smax z0.b, z0.b, #-58
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 16 x i8> undef, i8 -58, i32 0
   %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %cmp = icmp sgt <vscale x 16 x i8> %a, %splat
@@ -30,9 +33,10 @@ define <vscale x 16 x i8> @smax_i8_neg(<vscale x 16 x i8> %a) {
 }
 
 define <vscale x 8 x i16> @smax_i16_pos(<vscale x 8 x i16> %a) {
-; CHECK-LABEL: smax_i16_pos
-; CHECK: smax z0.h, z0.h, #27
-; CHECK-NEXT: ret
+; CHECK-LABEL: smax_i16_pos:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    smax z0.h, z0.h, #27
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 8 x i16> undef, i16 27, i32 0
   %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %cmp = icmp sgt <vscale x 8 x i16> %a, %splat
@@ -41,9 +45,10 @@ define <vscale x 8 x i16> @smax_i16_pos(<vscale x 8 x i16> %a) {
 }
 
 define <vscale x 8 x i16> @smax_i16_neg(<vscale x 8 x i16> %a) {
-; CHECK-LABEL: smax_i16_neg
-; CHECK: smax z0.h, z0.h, #-58
-; CHECK-NEXT: ret
+; CHECK-LABEL: smax_i16_neg:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    smax z0.h, z0.h, #-58
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 8 x i16> undef, i16 -58, i32 0
   %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %cmp = icmp sgt <vscale x 8 x i16> %a, %splat
@@ -53,7 +58,8 @@ define <vscale x 8 x i16> @smax_i16_neg(<vscale x 8 x i16> %a) {
 
 define <vscale x 8 x i16> @smax_i16_out_of_range(<vscale x 8 x i16> %a) {
 ; CHECK-LABEL: smax_i16_out_of_range:
-; CHECK:    mov w8, #257
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #257
 ; CHECK-NEXT:    mov z1.h, w8
 ; CHECK-NEXT:    ptrue p0.h
 ; CHECK-NEXT:    smax z0.h, p0/m, z0.h, z1.h
@@ -66,9 +72,10 @@ define <vscale x 8 x i16> @smax_i16_out_of_range(<vscale x 8 x i16> %a) {
 }
 
 define <vscale x 4 x i32> @smax_i32_pos(<vscale x 4 x i32> %a) {
-; CHECK-LABEL: smax_i32_pos
-; CHECK: smax z0.s, z0.s, #27
-; CHECK: ret
+; CHECK-LABEL: smax_i32_pos:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    smax z0.s, z0.s, #27
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 4 x i32> undef, i32 27, i32 0
   %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %cmp = icmp sgt <vscale x 4 x i32> %a, %splat
@@ -77,9 +84,10 @@ define <vscale x 4 x i32> @smax_i32_pos(<vscale x 4 x i32> %a) {
 }
 
 define <vscale x 4 x i32> @smax_i32_neg(<vscale x 4 x i32> %a) {
-; CHECK-LABEL: smax_i32_neg
-; CHECK: smax z0.s, z0.s, #-58
-; CHECK-NEXT: ret
+; CHECK-LABEL: smax_i32_neg:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    smax z0.s, z0.s, #-58
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 4 x i32> undef, i32 -58, i32 0
   %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %cmp = icmp sgt <vscale x 4 x i32> %a, %splat
@@ -89,7 +97,8 @@ define <vscale x 4 x i32> @smax_i32_neg(<vscale x 4 x i32> %a) {
 
 define <vscale x 4 x i32> @smax_i32_out_of_range(<vscale x 4 x i32> %a) {
 ; CHECK-LABEL: smax_i32_out_of_range:
-; CHECK:    mov w8, #-129
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #-129
 ; CHECK-NEXT:    mov z1.s, w8
 ; CHECK-NEXT:    ptrue p0.s
 ; CHECK-NEXT:    smax z0.s, p0/m, z0.s, z1.s
@@ -102,9 +111,10 @@ define <vscale x 4 x i32> @smax_i32_out_of_range(<vscale x 4 x i32> %a) {
 }
 
 define <vscale x 2 x i64> @smax_i64_pos(<vscale x 2 x i64> %a) {
-; CHECK-LABEL: smax_i64_pos
-; CHECK: smax z0.d, z0.d, #27
-; CHECK-NEXT: ret
+; CHECK-LABEL: smax_i64_pos:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    smax z0.d, z0.d, #27
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 2 x i64> undef, i64 27, i32 0
   %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %cmp = icmp sgt <vscale x 2 x i64> %a, %splat
@@ -113,9 +123,10 @@ define <vscale x 2 x i64> @smax_i64_pos(<vscale x 2 x i64> %a) {
 }
 
 define <vscale x 2 x i64> @smax_i64_neg(<vscale x 2 x i64> %a) {
-; CHECK-LABEL: smax_i64_neg
-; CHECK: smax z0.d, z0.d, #-58
-; CHECK-NEXT: ret
+; CHECK-LABEL: smax_i64_neg:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    smax z0.d, z0.d, #-58
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 2 x i64> undef, i64 -58, i32 0
   %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %cmp = icmp sgt <vscale x 2 x i64> %a, %splat
@@ -125,7 +136,8 @@ define <vscale x 2 x i64> @smax_i64_neg(<vscale x 2 x i64> %a) {
 
 define <vscale x 2 x i64> @smax_i64_out_of_range(<vscale x 2 x i64> %a) {
 ; CHECK-LABEL: smax_i64_out_of_range:
-; CHECK:    mov w8, #65535
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #65535
 ; CHECK-NEXT:    mov z1.d, x8
 ; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    smax z0.d, p0/m, z0.d, z1.d
@@ -141,9 +153,10 @@ define <vscale x 2 x i64> @smax_i64_out_of_range(<vscale x 2 x i64> %a) {
 ; SMIN
 ;
 define <vscale x 16 x i8> @smin_i8_pos(<vscale x 16 x i8> %a) {
-; CHECK-LABEL: smin_i8_pos
-; CHECK: smin z0.b, z0.b, #27
-; CHECK-NEXT: ret
+; CHECK-LABEL: smin_i8_pos:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    smin z0.b, z0.b, #27
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 16 x i8> undef, i8 27, i32 0
   %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %cmp = icmp slt <vscale x 16 x i8> %a, %splat
@@ -152,9 +165,10 @@ define <vscale x 16 x i8> @smin_i8_pos(<vscale x 16 x i8> %a) {
 }
 
 define <vscale x 16 x i8> @smin_i8_neg(<vscale x 16 x i8> %a) {
-; CHECK-LABEL: smin_i8_neg
-; CHECK: smin z0.b, z0.b, #-58
-; CHECK-NEXT: ret
+; CHECK-LABEL: smin_i8_neg:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    smin z0.b, z0.b, #-58
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 16 x i8> undef, i8 -58, i32 0
   %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %cmp = icmp slt <vscale x 16 x i8> %a, %splat
@@ -163,9 +177,10 @@ define <vscale x 16 x i8> @smin_i8_neg(<vscale x 16 x i8> %a) {
 }
 
 define <vscale x 8 x i16> @smin_i16_pos(<vscale x 8 x i16> %a) {
-; CHECK-LABEL: smin_i16_pos
-; CHECK: smin z0.h, z0.h, #27
-; CHECK-NEXT: ret
+; CHECK-LABEL: smin_i16_pos:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    smin z0.h, z0.h, #27
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 8 x i16> undef, i16 27, i32 0
   %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %cmp = icmp slt <vscale x 8 x i16> %a, %splat
@@ -174,9 +189,10 @@ define <vscale x 8 x i16> @smin_i16_pos(<vscale x 8 x i16> %a) {
 }
 
 define <vscale x 8 x i16> @smin_i16_neg(<vscale x 8 x i16> %a) {
-; CHECK-LABEL: smin_i16_neg
-; CHECK: smin z0.h, z0.h, #-58
-; CHECK-NEXT: ret
+; CHECK-LABEL: smin_i16_neg:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    smin z0.h, z0.h, #-58
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 8 x i16> undef, i16 -58, i32 0
   %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %cmp = icmp slt <vscale x 8 x i16> %a, %splat
@@ -186,7 +202,8 @@ define <vscale x 8 x i16> @smin_i16_neg(<vscale x 8 x i16> %a) {
 
 define <vscale x 8 x i16> @smin_i16_out_of_range(<vscale x 8 x i16> %a) {
 ; CHECK-LABEL: smin_i16_out_of_range:
-; CHECK:    mov w8, #257
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #257
 ; CHECK-NEXT:    mov z1.h, w8
 ; CHECK-NEXT:    ptrue p0.h
 ; CHECK-NEXT:    smin z0.h, p0/m, z0.h, z1.h
@@ -199,9 +216,10 @@ define <vscale x 8 x i16> @smin_i16_out_of_range(<vscale x 8 x i16> %a) {
 }
 
 define <vscale x 4 x i32> @smin_i32_pos(<vscale x 4 x i32> %a) {
-; CHECK-LABEL: smin_i32_pos
-; CHECK: smin z0.s, z0.s, #27
-; CHECK-NEXT: ret
+; CHECK-LABEL: smin_i32_pos:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    smin z0.s, z0.s, #27
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 4 x i32> undef, i32 27, i32 0
   %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %cmp = icmp slt <vscale x 4 x i32> %a, %splat
@@ -210,9 +228,10 @@ define <vscale x 4 x i32> @smin_i32_pos(<vscale x 4 x i32> %a) {
 }
 
 define <vscale x 4 x i32> @smin_i32_neg(<vscale x 4 x i32> %a) {
-; CHECK-LABEL: smin_i32_neg
-; CHECK: smin z0.s, z0.s, #-58
-; CHECK-NEXT: ret
+; CHECK-LABEL: smin_i32_neg:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    smin z0.s, z0.s, #-58
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 4 x i32> undef, i32 -58, i32 0
   %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %cmp = icmp slt <vscale x 4 x i32> %a, %splat
@@ -222,7 +241,8 @@ define <vscale x 4 x i32> @smin_i32_neg(<vscale x 4 x i32> %a) {
 
 define <vscale x 4 x i32> @smin_i32_out_of_range(<vscale x 4 x i32> %a) {
 ; CHECK-LABEL: smin_i32_out_of_range:
-; CHECK:    mov w8, #-129
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #-129
 ; CHECK-NEXT:    mov z1.s, w8
 ; CHECK-NEXT:    ptrue p0.s
 ; CHECK-NEXT:    smin z0.s, p0/m, z0.s, z1.s
@@ -235,9 +255,10 @@ define <vscale x 4 x i32> @smin_i32_out_of_range(<vscale x 4 x i32> %a) {
 }
 
 define <vscale x 2 x i64> @smin_i64_pos(<vscale x 2 x i64> %a) {
-; CHECK-LABEL: smin_i64_pos
-; CHECK: smin z0.d, z0.d, #27
-; CHECK-NEXT: ret
+; CHECK-LABEL: smin_i64_pos:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    smin z0.d, z0.d, #27
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 2 x i64> undef, i64 27, i32 0
   %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %cmp = icmp slt <vscale x 2 x i64> %a, %splat
@@ -246,9 +267,10 @@ define <vscale x 2 x i64> @smin_i64_pos(<vscale x 2 x i64> %a) {
 }
 
 define <vscale x 2 x i64> @smin_i64_neg(<vscale x 2 x i64> %a) {
-; CHECK-LABEL: smin_i64_neg
-; CHECK: smin z0.d, z0.d, #-58
-; CHECK-NEXT: ret
+; CHECK-LABEL: smin_i64_neg:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    smin z0.d, z0.d, #-58
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 2 x i64> undef, i64 -58, i32 0
   %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %cmp = icmp slt <vscale x 2 x i64> %a, %splat
@@ -258,7 +280,8 @@ define <vscale x 2 x i64> @smin_i64_neg(<vscale x 2 x i64> %a) {
 
 define <vscale x 2 x i64> @smin_i64_out_of_range(<vscale x 2 x i64> %a) {
 ; CHECK-LABEL: smin_i64_out_of_range:
-; CHECK:    mov w8, #65535
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #65535
 ; CHECK-NEXT:    mov z1.d, x8
 ; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    smin z0.d, p0/m, z0.d, z1.d
@@ -274,9 +297,10 @@ define <vscale x 2 x i64> @smin_i64_out_of_range(<vscale x 2 x i64> %a) {
 ; UMAX
 ;
 define <vscale x 16 x i8> @umax_i8_pos(<vscale x 16 x i8> %a) {
-; CHECK-LABEL: umax_i8_pos
-; CHECK: umax z0.b, z0.b, #27
-; CHECK-NEXT: ret
+; CHECK-LABEL: umax_i8_pos:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    umax z0.b, z0.b, #27
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 16 x i8> undef, i8 27, i32 0
   %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %cmp = icmp ugt <vscale x 16 x i8> %a, %splat
@@ -285,9 +309,10 @@ define <vscale x 16 x i8> @umax_i8_pos(<vscale x 16 x i8> %a) {
 }
 
 define <vscale x 16 x i8> @umax_i8_large(<vscale x 16 x i8> %a) {
-; CHECK-LABEL: umax_i8_large
-; CHECK: umax z0.b, z0.b, #129
-; CHECK-NEXT: ret
+; CHECK-LABEL: umax_i8_large:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    umax z0.b, z0.b, #129
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 16 x i8> undef, i8 129, i32 0
   %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %cmp = icmp ugt <vscale x 16 x i8> %a, %splat
@@ -296,9 +321,10 @@ define <vscale x 16 x i8> @umax_i8_large(<vscale x 16 x i8> %a) {
 }
 
 define <vscale x 8 x i16> @umax_i16_pos(<vscale x 8 x i16> %a) {
-; CHECK-LABEL: umax_i16_pos
-; CHECK: umax z0.h, z0.h, #27
-; CHECK-NEXT: ret
+; CHECK-LABEL: umax_i16_pos:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    umax z0.h, z0.h, #27
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 8 x i16> undef, i16 27, i32 0
   %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %cmp = icmp ugt <vscale x 8 x i16> %a, %splat
@@ -308,7 +334,8 @@ define <vscale x 8 x i16> @umax_i16_pos(<vscale x 8 x i16> %a) {
 
 define <vscale x 8 x i16> @umax_i16_out_of_range(<vscale x 8 x i16> %a) {
 ; CHECK-LABEL: umax_i16_out_of_range:
-; CHECK:    mov w8, #257
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #257
 ; CHECK-NEXT:    mov z1.h, w8
 ; CHECK-NEXT:    ptrue p0.h
 ; CHECK-NEXT:    umax z0.h, p0/m, z0.h, z1.h
@@ -321,9 +348,10 @@ define <vscale x 8 x i16> @umax_i16_out_of_range(<vscale x 8 x i16> %a) {
 }
 
 define <vscale x 4 x i32> @umax_i32_pos(<vscale x 4 x i32> %a) {
-; CHECK-LABEL: umax_i32_pos
-; CHECK: umax z0.s, z0.s, #27
-; CHECK-NEXT: ret
+; CHECK-LABEL: umax_i32_pos:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    umax z0.s, z0.s, #27
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 4 x i32> undef, i32 27, i32 0
   %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %cmp = icmp ugt <vscale x 4 x i32> %a, %splat
@@ -333,7 +361,8 @@ define <vscale x 4 x i32> @umax_i32_pos(<vscale x 4 x i32> %a) {
 
 define <vscale x 4 x i32> @umax_i32_out_of_range(<vscale x 4 x i32> %a) {
 ; CHECK-LABEL: umax_i32_out_of_range:
-; CHECK:    mov w8, #257
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #257
 ; CHECK-NEXT:    mov z1.s, w8
 ; CHECK-NEXT:    ptrue p0.s
 ; CHECK-NEXT:    umax z0.s, p0/m, z0.s, z1.s
@@ -346,9 +375,10 @@ define <vscale x 4 x i32> @umax_i32_out_of_range(<vscale x 4 x i32> %a) {
 }
 
 define <vscale x 2 x i64> @umax_i64_pos(<vscale x 2 x i64> %a) {
-; CHECK-LABEL: umax_i64_pos
-; CHECK: umax z0.d, z0.d, #27
-; CHECK-NEXT: ret
+; CHECK-LABEL: umax_i64_pos:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    umax z0.d, z0.d, #27
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 2 x i64> undef, i64 27, i32 0
   %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %cmp = icmp ugt <vscale x 2 x i64> %a, %splat
@@ -358,7 +388,8 @@ define <vscale x 2 x i64> @umax_i64_pos(<vscale x 2 x i64> %a) {
 
 define <vscale x 2 x i64> @umax_i64_out_of_range(<vscale x 2 x i64> %a) {
 ; CHECK-LABEL: umax_i64_out_of_range:
-; CHECK:    mov w8, #65535
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #65535
 ; CHECK-NEXT:    mov z1.d, x8
 ; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    umax z0.d, p0/m, z0.d, z1.d
@@ -374,9 +405,10 @@ define <vscale x 2 x i64> @umax_i64_out_of_range(<vscale x 2 x i64> %a) {
 ; UMIN
 ;
 define <vscale x 16 x i8> @umin_i8_pos(<vscale x 16 x i8> %a) {
-; CHECK-LABEL: umin_i8_pos
-; CHECK: umin z0.b, z0.b, #27
-; CHECK-NEXT: ret
+; CHECK-LABEL: umin_i8_pos:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    umin z0.b, z0.b, #27
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 16 x i8> undef, i8 27, i32 0
   %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %cmp = icmp ult <vscale x 16 x i8> %a, %splat
@@ -385,9 +417,10 @@ define <vscale x 16 x i8> @umin_i8_pos(<vscale x 16 x i8> %a) {
 }
 
 define <vscale x 16 x i8> @umin_i8_large(<vscale x 16 x i8> %a) {
-; CHECK-LABEL: umin_i8_large
-; CHECK: umin z0.b, z0.b, #129
-; CHECK-NEXT: ret
+; CHECK-LABEL: umin_i8_large:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    umin z0.b, z0.b, #129
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 16 x i8> undef, i8 129, i32 0
   %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %cmp = icmp ult <vscale x 16 x i8> %a, %splat
@@ -396,9 +429,10 @@ define <vscale x 16 x i8> @umin_i8_large(<vscale x 16 x i8> %a) {
 }
 
 define <vscale x 8 x i16> @umin_i16_pos(<vscale x 8 x i16> %a) {
-; CHECK-LABEL: umin_i16_pos
-; CHECK: umin z0.h, z0.h, #27
-; CHECK-NEXT: ret
+; CHECK-LABEL: umin_i16_pos:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    umin z0.h, z0.h, #27
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 8 x i16> undef, i16 27, i32 0
   %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %cmp = icmp ult <vscale x 8 x i16> %a, %splat
@@ -408,7 +442,8 @@ define <vscale x 8 x i16> @umin_i16_pos(<vscale x 8 x i16> %a) {
 
 define <vscale x 8 x i16> @umin_i16_out_of_range(<vscale x 8 x i16> %a) {
 ; CHECK-LABEL: umin_i16_out_of_range:
-; CHECK:    mov w8, #257
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #257
 ; CHECK-NEXT:    mov z1.h, w8
 ; CHECK-NEXT:    ptrue p0.h
 ; CHECK-NEXT:    umin z0.h, p0/m, z0.h, z1.h
@@ -421,9 +456,10 @@ define <vscale x 8 x i16> @umin_i16_out_of_range(<vscale x 8 x i16> %a) {
 }
 
 define <vscale x 4 x i32> @umin_i32_pos(<vscale x 4 x i32> %a) {
-; CHECK-LABEL: umin_i32_pos
-; CHECK: umin z0.s, z0.s, #27
-; CHECK-NEXT: ret
+; CHECK-LABEL: umin_i32_pos:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    umin z0.s, z0.s, #27
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 4 x i32> undef, i32 27, i32 0
   %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %cmp = icmp ult <vscale x 4 x i32> %a, %splat
@@ -433,7 +469,8 @@ define <vscale x 4 x i32> @umin_i32_pos(<vscale x 4 x i32> %a) {
 
 define <vscale x 4 x i32> @umin_i32_out_of_range(<vscale x 4 x i32> %a) {
 ; CHECK-LABEL: umin_i32_out_of_range:
-; CHECK:    mov w8, #257
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #257
 ; CHECK-NEXT:    mov z1.s, w8
 ; CHECK-NEXT:    ptrue p0.s
 ; CHECK-NEXT:    umin z0.s, p0/m, z0.s, z1.s
@@ -446,9 +483,10 @@ define <vscale x 4 x i32> @umin_i32_out_of_range(<vscale x 4 x i32> %a) {
 }
 
 define <vscale x 2 x i64> @umin_i64_pos(<vscale x 2 x i64> %a) {
-; CHECK-LABEL: umin_i64_pos
-; CHECK: umin z0.d, z0.d, #27
-; CHECK-NEXT: ret
+; CHECK-LABEL: umin_i64_pos:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    umin z0.d, z0.d, #27
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 2 x i64> undef, i64 27, i32 0
   %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %cmp = icmp ult <vscale x 2 x i64> %a, %splat
@@ -458,7 +496,8 @@ define <vscale x 2 x i64> @umin_i64_pos(<vscale x 2 x i64> %a) {
 
 define <vscale x 2 x i64> @umin_i64_out_of_range(<vscale x 2 x i64> %a) {
 ; CHECK-LABEL: umin_i64_out_of_range:
-; CHECK:    mov w8, #65535
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #65535
 ; CHECK-NEXT:    mov z1.d, x8
 ; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    umin z0.d, p0/m, z0.d, z1.d
@@ -474,9 +513,10 @@ define <vscale x 2 x i64> @umin_i64_out_of_range(<vscale x 2 x i64> %a) {
 ; MUL
 ;
 define <vscale x 16 x i8> @mul_i8_neg(<vscale x 16 x i8> %a) {
-; CHECK-LABEL: mul_i8_neg
-; CHECK: mul z0.b, z0.b, #-17
-; CHECK-NEXT: ret
+; CHECK-LABEL: mul_i8_neg:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mul z0.b, z0.b, #-17
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 16 x i8> undef, i8 -17, i32 0
   %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %res = mul <vscale x 16 x i8> %a, %splat
@@ -484,9 +524,10 @@ define <vscale x 16 x i8> @mul_i8_neg(<vscale x 16 x i8> %a) {
 }
 
 define <vscale x 16 x i8> @mul_i8_pos(<vscale x 16 x i8> %a) {
-; CHECK-LABEL: mul_i8_pos
-; CHECK: mul z0.b, z0.b, #105
-; CHECK-NEXT: ret
+; CHECK-LABEL: mul_i8_pos:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mul z0.b, z0.b, #105
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 16 x i8> undef, i8 105, i32 0
   %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %res = mul <vscale x 16 x i8> %a, %splat
@@ -494,9 +535,10 @@ define <vscale x 16 x i8> @mul_i8_pos(<vscale x 16 x i8> %a) {
 }
 
 define <vscale x 8 x i16> @mul_i16_neg(<vscale x 8 x i16> %a) {
-; CHECK-LABEL: mul_i16_neg
-; CHECK: mul z0.h, z0.h, #-17
-; CHECK-NEXT: ret
+; CHECK-LABEL: mul_i16_neg:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mul z0.h, z0.h, #-17
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 8 x i16> undef, i16 -17, i32 0
   %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %res = mul <vscale x 8 x i16> %a, %splat
@@ -504,9 +546,10 @@ define <vscale x 8 x i16> @mul_i16_neg(<vscale x 8 x i16> %a) {
 }
 
 define <vscale x 8 x i16> @mul_i16_pos(<vscale x 8 x i16> %a) {
-; CHECK-LABEL: mul_i16_pos
-; CHECK: mul z0.h, z0.h, #105
-; CHECK-NEXT: ret
+; CHECK-LABEL: mul_i16_pos:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mul z0.h, z0.h, #105
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 8 x i16> undef, i16 105, i32 0
   %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %res = mul <vscale x 8 x i16> %a, %splat
@@ -514,9 +557,10 @@ define <vscale x 8 x i16> @mul_i16_pos(<vscale x 8 x i16> %a) {
 }
 
 define <vscale x 4 x i32> @mul_i32_neg(<vscale x 4 x i32> %a) {
-; CHECK-LABEL: mul_i32_neg
-; CHECK: mul z0.s, z0.s, #-17
-; CHECK-NEXT: ret
+; CHECK-LABEL: mul_i32_neg:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mul z0.s, z0.s, #-17
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 4 x i32> undef, i32 -17, i32 0
   %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %res = mul <vscale x 4 x i32> %a, %splat
@@ -524,9 +568,10 @@ define <vscale x 4 x i32> @mul_i32_neg(<vscale x 4 x i32> %a) {
 }
 
 define <vscale x 4 x i32> @mul_i32_pos(<vscale x 4 x i32> %a) {
-; CHECK-LABEL: mul_i32_pos
-; CHECK: mul z0.s, z0.s, #105
-; CHECK-NEXT: ret
+; CHECK-LABEL: mul_i32_pos:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mul z0.s, z0.s, #105
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 4 x i32> undef, i32 105, i32 0
   %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %res = mul <vscale x 4 x i32> %a, %splat
@@ -534,9 +579,10 @@ define <vscale x 4 x i32> @mul_i32_pos(<vscale x 4 x i32> %a) {
 }
 
 define <vscale x 2 x i64> @mul_i64_neg(<vscale x 2 x i64> %a) {
-; CHECK-LABEL: mul_i64_neg
-; CHECK: mul z0.d, z0.d, #-17
-; CHECK-NEXT: ret
+; CHECK-LABEL: mul_i64_neg:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mul z0.d, z0.d, #-17
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 2 x i64> undef, i64 -17, i32 0
   %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %res = mul <vscale x 2 x i64> %a, %splat
@@ -544,9 +590,10 @@ define <vscale x 2 x i64> @mul_i64_neg(<vscale x 2 x i64> %a) {
 }
 
 define <vscale x 2 x i64> @mul_i64_pos(<vscale x 2 x i64> %a) {
-; CHECK-LABEL: mul_i64_pos
-; CHECK: mul z0.d, z0.d, #105
-; CHECK-NEXT: ret
+; CHECK-LABEL: mul_i64_pos:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mul z0.d, z0.d, #105
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 2 x i64> undef, i64 105, i32 0
   %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %res = mul <vscale x 2 x i64> %a, %splat
@@ -554,11 +601,13 @@ define <vscale x 2 x i64> @mul_i64_pos(<vscale x 2 x i64> %a) {
 }
 
 define <vscale x 8 x i16> @mul_i16_range(<vscale x 8 x i16> %a) {
-; CHECK-LABEL: mul_i16_range
-; CHECK: mov w[[W:[0-9]+]], #255
-; CHECK-NEXT: mov z1.h, w[[W]]
-; CHECK: ptrue p0.h
-; CHECK-NEXT: mul z0.h, p0/m, z0.h, z1.h
+; CHECK-LABEL: mul_i16_range:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #255
+; CHECK-NEXT:    mov z1.h, w8
+; CHECK-NEXT:    ptrue p0.h
+; CHECK-NEXT:    mul z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 8 x i16> undef, i16 255, i32 0
   %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %res = mul <vscale x 8 x i16> %a, %splat
@@ -566,11 +615,13 @@ define <vscale x 8 x i16> @mul_i16_range(<vscale x 8 x i16> %a) {
 }
 
 define <vscale x 4 x i32> @mul_i32_range(<vscale x 4 x i32> %a) {
-; CHECK-LABEL: mul_i32_range
-; CHECK: mov w[[W:[0-9]+]], #255
-; CHECK-NEXT: mov z1.s, w[[W]]
-; CHECK: ptrue p0.s
-; CHECK-NEXT: mul z0.s, p0/m, z0.s, z1.s
+; CHECK-LABEL: mul_i32_range:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #255
+; CHECK-NEXT:    mov z1.s, w8
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    mul z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 4 x i32> undef, i32 255, i32 0
   %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %res = mul <vscale x 4 x i32> %a, %splat
@@ -578,11 +629,13 @@ define <vscale x 4 x i32> @mul_i32_range(<vscale x 4 x i32> %a) {
 }
 
 define <vscale x 2 x i64> @mul_i64_range(<vscale x 2 x i64> %a) {
-; CHECK-LABEL: mul_i64_range
-; CHECK: mov w[[W:[0-9]+]], #255
-; CHECK-NEXT: mov z1.d, x[[W]]
-; CHECK: ptrue p0.d
-; CHECK-NEXT: mul z0.d, p0/m, z0.d, z1.d
+; CHECK-LABEL: mul_i64_range:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #255
+; CHECK-NEXT:    mov z1.d, x8
+; CHECK-NEXT:    ptrue p0.d
+; CHECK-NEXT:    mul z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 2 x i64> undef, i64 255, i32 0
   %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %res = mul <vscale x 2 x i64> %a, %splat
@@ -592,40 +645,44 @@ define <vscale x 2 x i64> @mul_i64_range(<vscale x 2 x i64> %a) {
 ; ASR
 
 define <vscale x 16 x i8> @asr_i8(<vscale x 16 x i8> %a){
-; CHECK-LABEL: @asr_i8
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
-  %elt = insertelement <vscale x 16 x i8> undef, i8 8, i32 0
+; CHECK-LABEL: asr_i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    asr z0.b, z0.b, #7
+; CHECK-NEXT:    ret
+  %elt = insertelement <vscale x 16 x i8> undef, i8 7, i32 0
   %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %lshr = ashr <vscale x 16 x i8> %a, %splat
   ret <vscale x 16 x i8> %lshr
 }
 
 define <vscale x 8 x i16> @asr_i16(<vscale x 8 x i16> %a){
-; CHECK-LABEL: @asr_i16
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
-  %elt = insertelement <vscale x 8 x i16> undef, i16 16, i32 0
+; CHECK-LABEL: asr_i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    asr z0.h, z0.h, #15
+; CHECK-NEXT:    ret
+  %elt = insertelement <vscale x 8 x i16> undef, i16 15, i32 0
   %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %ashr = ashr <vscale x 8 x i16> %a, %splat
   ret <vscale x 8 x i16> %ashr
 }
 
 define <vscale x 4 x i32> @asr_i32(<vscale x 4 x i32> %a){
-; CHECK-LABEL: @asr_i32
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
-  %elt = insertelement <vscale x 4 x i32> undef, i32 32, i32 0
+; CHECK-LABEL: asr_i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    asr z0.s, z0.s, #31
+; CHECK-NEXT:    ret
+  %elt = insertelement <vscale x 4 x i32> undef, i32 31, i32 0
   %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %ashr = ashr <vscale x 4 x i32> %a, %splat
   ret <vscale x 4 x i32> %ashr
 }
 
 define <vscale x 2 x i64> @asr_i64(<vscale x 2 x i64> %a){
-; CHECK-LABEL: @asr_i64
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
-  %elt = insertelement <vscale x 2 x i64> undef, i64 64, i32 0
+; CHECK-LABEL: asr_i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    asr z0.d, z0.d, #63
+; CHECK-NEXT:    ret
+  %elt = insertelement <vscale x 2 x i64> undef, i64 63, i32 0
   %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %ashr = ashr <vscale x 2 x i64> %a, %splat
   ret <vscale x 2 x i64> %ashr
@@ -634,9 +691,10 @@ define <vscale x 2 x i64> @asr_i64(<vscale x 2 x i64> %a){
 ; LSL
 
 define <vscale x 16 x i8> @lsl_i8(<vscale x 16 x i8> %a){
-; CHECK-LABEL: @lsl_i8
-; CHECK-DAG: lsl z0.b, z0.b, #7
-; CHECK-NEXT: ret
+; CHECK-LABEL: lsl_i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsl z0.b, z0.b, #7
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 16 x i8> undef, i8 7, i32 0
   %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %shl = shl <vscale x 16 x i8> %a, %splat
@@ -644,9 +702,10 @@ define <vscale x 16 x i8> @lsl_i8(<vscale x 16 x i8> %a){
 }
 
 define <vscale x 8 x i16> @lsl_i16(<vscale x 8 x i16> %a){
-; CHECK-LABEL: @lsl_i16
-; CHECK-DAG: lsl z0.h, z0.h, #15
-; CHECK-NEXT: ret
+; CHECK-LABEL: lsl_i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsl z0.h, z0.h, #15
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 8 x i16> undef, i16 15, i32 0
   %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %shl = shl <vscale x 8 x i16> %a, %splat
@@ -654,9 +713,10 @@ define <vscale x 8 x i16> @lsl_i16(<vscale x 8 x i16> %a){
 }
 
 define <vscale x 4 x i32> @lsl_i32(<vscale x 4 x i32> %a){
-; CHECK-LABEL: @lsl_i32
-; CHECK-DAG: lsl z0.s, z0.s, #31
-; CHECK-NEXT: ret
+; CHECK-LABEL: lsl_i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsl z0.s, z0.s, #31
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 4 x i32> undef, i32 31, i32 0
   %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %shl = shl <vscale x 4 x i32> %a, %splat
@@ -664,9 +724,10 @@ define <vscale x 4 x i32> @lsl_i32(<vscale x 4 x i32> %a){
 }
 
 define <vscale x 2 x i64> @lsl_i64(<vscale x 2 x i64> %a){
-; CHECK-LABEL: @lsl_i64
-; CHECK-DAG: lsl z0.d, z0.d, #63
-; CHECK-NEXT: ret
+; CHECK-LABEL: lsl_i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsl z0.d, z0.d, #63
+; CHECK-NEXT:    ret
   %elt = insertelement <vscale x 2 x i64> undef, i64 63, i32 0
   %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %shl = shl <vscale x 2 x i64> %a, %splat
@@ -676,40 +737,44 @@ define <vscale x 2 x i64> @lsl_i64(<vscale x 2 x i64> %a){
 ; LSR
 
 define <vscale x 16 x i8> @lsr_i8(<vscale x 16 x i8> %a){
-; CHECK-LABEL: @lsr_i8
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
-  %elt = insertelement <vscale x 16 x i8> undef, i8 8, i32 0
+; CHECK-LABEL: lsr_i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsr z0.b, z0.b, #7
+; CHECK-NEXT:    ret
+  %elt = insertelement <vscale x 16 x i8> undef, i8 7, i32 0
   %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %lshr = lshr <vscale x 16 x i8> %a, %splat
   ret <vscale x 16 x i8> %lshr
 }
 
 define <vscale x 8 x i16> @lsr_i16(<vscale x 8 x i16> %a){
-; CHECK-LABEL: @lsr_i16
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
-  %elt = insertelement <vscale x 8 x i16> undef, i16 16, i32 0
+; CHECK-LABEL: lsr_i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsr z0.h, z0.h, #15
+; CHECK-NEXT:    ret
+  %elt = insertelement <vscale x 8 x i16> undef, i16 15, i32 0
   %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %lshr = lshr <vscale x 8 x i16> %a, %splat
   ret <vscale x 8 x i16> %lshr
 }
 
 define <vscale x 4 x i32> @lsr_i32(<vscale x 4 x i32> %a){
-; CHECK-LABEL: @lsr_i32
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
-  %elt = insertelement <vscale x 4 x i32> undef, i32 32, i32 0
+; CHECK-LABEL: lsr_i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsr z0.s, z0.s, #31
+; CHECK-NEXT:    ret
+  %elt = insertelement <vscale x 4 x i32> undef, i32 31, i32 0
   %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %lshr = lshr <vscale x 4 x i32> %a, %splat
   ret <vscale x 4 x i32> %lshr
 }
 
 define <vscale x 2 x i64> @lsr_i64(<vscale x 2 x i64> %a){
-; CHECK-LABEL: @lsr_i64
-; CHECK: // %bb.0:
-; CHECK-NEXT: ret
-  %elt = insertelement <vscale x 2 x i64> undef, i64 64, i32 0
+; CHECK-LABEL: lsr_i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsr z0.d, z0.d, #63
+; CHECK-NEXT:    ret
+  %elt = insertelement <vscale x 2 x i64> undef, i64 63, i32 0
   %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %lshr = lshr <vscale x 2 x i64> %a, %splat
   ret <vscale x 2 x i64> %lshr