* gcc/config/arm/iterators.md (SDF): New mode iterator.

	(V_if_elem): Add support for SF and DF modes.
	(V_reg): Likewise.
	(F_constraint): New mode iterator attribute.
	(F_fma_type): Likewise.
	config/arm/vfp.md (fma<SDF:mode>4): New pattern.
	(*fmsub<SDF:mode>4): Likewise.
	(*fmnsub<SDF:mode>4): Likewise.
	(*fmnadd<SDF:mode>4): Likewise.
	* gcc/testsuite/gcc.target/arm/fma-sp.c: New testcase.
	* gcc/testsuite/gcc.target/arm/fma.c: Likewise.
	* gcc/testsuite/gcc.target/arm/fma.h: Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@189283 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 48015ae..2a891e3 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,15 @@
+2012-07-05  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
+
+       * config/arm/iterators.md (SDF): New mode iterator.
+       (V_if_elem): Add support for SF and DF modes.
+       (V_reg): Likewise.
+       (F_constraint): New mode iterator attribute.
+       (F_fma_type): Likewise.
+       config/arm/vfp.md (fma<SDF:mode>4): New pattern.
+       (*fmsub<SDF:mode>4): Likewise.
+       (*fmnsub<SDF:mode>4): Likewise.
+       (*fmnadd<SDF:mode>4): Likewise.
+
 2012-07-04  Uros Bizjak  <ubizjak@gmail.com>
 
        * expmed.c (expand_mult): Initialize coeff and is_neg.

diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 795a5ee..def8d9f 100644 (file)
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -42,6 +42,9 @@
 ;; A list of the 32bit and 64bit integer modes
 (define_mode_iterator SIDI [SI DI])
 
+;; A list of modes which the VFP unit can handle
+(define_mode_iterator SDF [(SF "TARGET_VFP") (DF "TARGET_VFP_DOUBLE")])
+
 ;; Integer element sizes implemented by IWMMXT.
 (define_mode_iterator VMMX [V2SI V4HI V8QI])
 
@@ -245,7 +248,8 @@
                          (V4HI "P") (V8HI  "q")
                          (V2SI "P") (V4SI  "q")
                          (V2SF "P") (V4SF  "q")
-                         (DI   "P") (V2DI  "q")])
+                         (DI   "P") (V2DI  "q")
+                         (SF   "")  (DF    "P")])
 
 ;; Wider modes with the same number of elements.
 (define_mode_attr V_widen [(V8QI "V8HI") (V4HI "V4SI") (V2SI "V2DI")])
@@ -303,7 +307,8 @@
                  (V4HI "i16") (V8HI  "i16")
                              (V2SI "i32") (V4SI  "i32")
                              (DI   "i64") (V2DI  "i64")
-                 (V2SF "f32") (V4SF  "f32")])
+                 (V2SF "f32") (V4SF  "f32")
+                 (SF "f32") (DF "f64")])
 
 ;; Same, but for operations which work on signed values.
 (define_mode_attr V_s_elem [(V8QI "s8")  (V16QI "s8")
@@ -423,6 +428,10 @@
 ;; Mode attribute for vshll.
 (define_mode_attr V_innermode [(V8QI "QI") (V4HI "HI") (V2SI "SI")])
 
+;; Mode attributes used for fused-multiply-accumulate VFP support
+(define_mode_attr F_constraint [(SF "t") (DF "w")])
+(define_mode_attr F_fma_type [(SF "fmacs") (DF "fmacd")])
+
 ;;----------------------------------------------------------------------------
 ;; Code attributes
 ;;----------------------------------------------------------------------------

diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md
index 2061414..3d18ecb 100644 (file)
--- a/gcc/config/arm/vfp.md
+++ b/gcc/config/arm/vfp.md
@@ -890,6 +890,54 @@
    (set_attr "type" "fmacd")]
 )
 
+;; Fused-multiply-accumulate
+
+(define_insn "fma<SDF:mode>4"
+  [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
+        (fma:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
+                (match_operand:SDF 2 "register_operand" "<F_constraint>")
+                (match_operand:SDF 3 "register_operand" "0")))]
+  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
+  "vfma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
+  [(set_attr "predicable" "yes")
+   (set_attr "type" "<F_fma_type>")]
+)
+
+(define_insn "*fmsub<SDF:mode>4"
+  [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
+       (fma:SDF (neg:SDF (match_operand:SDF 1 "register_operand"
+                                            "<F_constraint>"))
+                (match_operand:SDF 2 "register_operand" "<F_constraint>")
+                (match_operand:SDF 3 "register_operand" "0")))]
+  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
+  "vfms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
+  [(set_attr "predicable" "yes")
+   (set_attr "type" "<F_fma_type>")]
+)
+
+(define_insn "*fnmsub<SDF:mode>4"
+  [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
+       (fma:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
+                (match_operand:SDF 2 "register_operand" "<F_constraint>")
+                (neg:SDF (match_operand:SDF 3 "register_operand" "0"))))]
+  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
+  "vfnms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
+  [(set_attr "predicable" "yes")
+   (set_attr "type" "<F_fma_type>")]
+)
+
+(define_insn "*fnmadd<SDF:mode>4"
+  [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
+       (fma:SDF (neg:SDF (match_operand:SDF 1 "register_operand"
+                                              "<F_constraint>"))
+                (match_operand:SDF 2 "register_operand" "<F_constraint>")
+                (neg:SDF (match_operand:SDF 3 "register_operand" "0"))))]
+  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
+  "vfnma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
+  [(set_attr "predicable" "yes")
+   (set_attr "type" "<F_fma_type>")]
+)
+
 
 ;; Conversion routines
 

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index cdeac30..1b88564 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2012-07-05  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
+
+       * gcc.target/arm/fma-sp.c: New testcase.
+       * gcc.target/arm/fma.c: Likewise.
+       * gcc.target/arm/fma.h: Likewise.
+
 2012-07-04  Jason Merrill  <jason@redhat.com>
 
        PR c++/53848