phy: mediatek: mipi: mt8173: use GENMASK to generate bits mask

Use GENMASK() macro to generate bits mask

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220920090038.15133-14-chunfeng.yun@mediatek.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c
index 7a84795..5c257d6 100644 (file)
--- a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c
+++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c
@@ -9,9 +9,9 @@
 #define MIPITX_DSI_CON         0x00
 #define RG_DSI_LDOCORE_EN              BIT(0)
 #define RG_DSI_CKG_LDOOUT_EN           BIT(1)
-#define RG_DSI_BCLK_SEL                        (3 << 2)
-#define RG_DSI_LD_IDX_SEL              (7 << 4)
-#define RG_DSI_PHYCLK_SEL              (2 << 8)
+#define RG_DSI_BCLK_SEL                        GENMASK(3, 2)
+#define RG_DSI_LD_IDX_SEL              GENMASK(6, 4)
+#define RG_DSI_PHYCLK_SEL              GENMASK(9, 8)
 #define RG_DSI_DSICLK_FREQ_SEL         BIT(10)
 #define RG_DSI_LPTX_CLMP_EN            BIT(11)
 
@@ -27,41 +27,46 @@
 #define RG_DSI_LNTx_LPTX_IMINUS                BIT(4)
 #define RG_DSI_LNTx_LPCD_IPLUS         BIT(5)
 #define RG_DSI_LNTx_LPCD_IMINUS                BIT(6)
-#define RG_DSI_LNTx_RT_CODE            (0xf << 8)
+#define RG_DSI_LNTx_RT_CODE            GENMASK(11, 8)
 
 #define MIPITX_DSI_TOP_CON     0x40
 #define RG_DSI_LNT_INTR_EN             BIT(0)
 #define RG_DSI_LNT_HS_BIAS_EN          BIT(1)
 #define RG_DSI_LNT_IMP_CAL_EN          BIT(2)
 #define RG_DSI_LNT_TESTMODE_EN         BIT(3)
-#define RG_DSI_LNT_IMP_CAL_CODE                (0xf << 4)
-#define RG_DSI_LNT_AIO_SEL             (7 << 8)
+#define RG_DSI_LNT_IMP_CAL_CODE                GENMASK(7, 4)
+#define RG_DSI_LNT_AIO_SEL             GENMASK(10, 8)
 #define RG_DSI_PAD_TIE_LOW_EN          BIT(11)
 #define RG_DSI_DEBUG_INPUT_EN          BIT(12)
-#define RG_DSI_PRESERVE                        (7 << 13)
+#define RG_DSI_PRESERVE                        GENMASK(15, 13)
 
 #define MIPITX_DSI_BG_CON      0x44
 #define RG_DSI_BG_CORE_EN              BIT(0)
 #define RG_DSI_BG_CKEN                 BIT(1)
-#define RG_DSI_BG_DIV                  (0x3 << 2)
+#define RG_DSI_BG_DIV                  GENMASK(3, 2)
 #define RG_DSI_BG_FAST_CHARGE          BIT(4)
-#define RG_DSI_VOUT_MSK                        (0x3ffff << 5)
-#define RG_DSI_V12_SEL                 (7 << 5)
-#define RG_DSI_V10_SEL                 (7 << 8)
-#define RG_DSI_V072_SEL                        (7 << 11)
-#define RG_DSI_V04_SEL                 (7 << 14)
-#define RG_DSI_V032_SEL                        (7 << 17)
-#define RG_DSI_V02_SEL                 (7 << 20)
-#define RG_DSI_BG_R1_TRIM              (0xf << 24)
-#define RG_DSI_BG_R2_TRIM              (0xf << 28)
+
+#define RG_DSI_V12_SEL                 GENMASK(7, 5)
+#define RG_DSI_V10_SEL                 GENMASK(10, 8)
+#define RG_DSI_V072_SEL                        GENMASK(13, 11)
+#define RG_DSI_V04_SEL                 GENMASK(16, 14)
+#define RG_DSI_V032_SEL                        GENMASK(19, 17)
+#define RG_DSI_V02_SEL                 GENMASK(22, 20)
+#define RG_DSI_VOUT_MSK                        \
+               (RG_DSI_V12_SEL | RG_DSI_V10_SEL | RG_DSI_V072_SEL | \
+                RG_DSI_V04_SEL | RG_DSI_V032_SEL | RG_DSI_V02_SEL)
+#define RG_DSI_BG_R1_TRIM              GENMASK(27, 24)
+#define RG_DSI_BG_R2_TRIM              GENMASK(31, 28)
 
 #define MIPITX_DSI_PLL_CON0    0x50
 #define RG_DSI_MPPLL_PLL_EN            BIT(0)
-#define RG_DSI_MPPLL_DIV_MSK           (0x1ff << 1)
-#define RG_DSI_MPPLL_PREDIV            (3 << 1)
-#define RG_DSI_MPPLL_TXDIV0            (3 << 3)
-#define RG_DSI_MPPLL_TXDIV1            (3 << 5)
-#define RG_DSI_MPPLL_POSDIV            (7 << 7)
+#define RG_DSI_MPPLL_PREDIV            GENMASK(2, 1)
+#define RG_DSI_MPPLL_TXDIV0            GENMASK(4, 3)
+#define RG_DSI_MPPLL_TXDIV1            GENMASK(6, 5)
+#define RG_DSI_MPPLL_POSDIV            GENMASK(9, 7)
+#define RG_DSI_MPPLL_DIV_MSK           \
+               (RG_DSI_MPPLL_PREDIV | RG_DSI_MPPLL_TXDIV0 | \
+                RG_DSI_MPPLL_TXDIV1 | RG_DSI_MPPLL_POSDIV)
 #define RG_DSI_MPPLL_MONVC_EN          BIT(10)
 #define RG_DSI_MPPLL_MONREF_EN         BIT(11)
 #define RG_DSI_MPPLL_VOD_EN            BIT(12)
@@ -70,12 +75,12 @@
 #define RG_DSI_MPPLL_SDM_FRA_EN                BIT(0)
 #define RG_DSI_MPPLL_SDM_SSC_PH_INIT   BIT(1)
 #define RG_DSI_MPPLL_SDM_SSC_EN                BIT(2)
-#define RG_DSI_MPPLL_SDM_SSC_PRD       (0xffff << 16)
+#define RG_DSI_MPPLL_SDM_SSC_PRD       GENMASK(31, 16)
 
 #define MIPITX_DSI_PLL_CON2    0x58
 
 #define MIPITX_DSI_PLL_TOP     0x64
-#define RG_DSI_MPPLL_PRESERVE          (0xff << 8)
+#define RG_DSI_MPPLL_PRESERVE          GENMASK(15, 8)
 
 #define MIPITX_DSI_PLL_PWR     0x68
 #define RG_DSI_MPPLL_SDM_PWR_ON                BIT(0)