""
"ror%.b %1,%0")
\f
+
+;; Bit set/clear in memory byte.
+
+;; set bit, bit number is int
+(define_insn "bsetmemqi"
+ [(set (match_operand:QI 0 "memory_operand" "+m")
+ (ior:QI (subreg:QI (ashift:SI (const_int 1)
+ (match_operand:SI 1 "general_operand" "d")) 0)
+ (match_dup 0)))]
+ ""
+ "*
+{
+ CC_STATUS_INIT;
+ return \"bset %1,%0\";
+}")
+
+;; set bit, bit number is (sign/zero)_extended from HImode/QImode
+(define_insn ""
+ [(set (match_operand:QI 0 "memory_operand" "+m")
+ (ior:QI (subreg:QI (ashift:SI (const_int 1)
+ (match_operator:SI 2 "extend_operator"
+ [(match_operand 1 "general_operand" "d")])) 0)
+ (match_dup 0)))]
+ ""
+ "*
+{
+ CC_STATUS_INIT;
+ return \"bset %1,%0\";
+}")
+
+;; clear bit, bit number is int
+(define_insn "bclrmemqi"
+ [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
+ (const_int 1)
+ (minus:SI (const_int 7)
+ (match_operand:SI 1 "general_operand" "d")))
+ (const_int 0))]
+ ""
+ "*
+{
+ CC_STATUS_INIT;
+ return \"bclr %1,%0\";
+}")
+
+;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
+(define_insn ""
+ [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
+ (const_int 1)
+ (minus:SI (const_int 7)
+ (match_operator:SI 2 "extend_operator"
+ [(match_operand 1 "general_operand" "d")])))
+ (const_int 0))]
+ ""
+ "*
+{
+ CC_STATUS_INIT;
+ return \"bclr %1,%0\";
+}")
+
;; Special cases of bit-field insns which we should
;; recognize in preference to the general case.
;; These handle aligned 8-bit and 16-bit fields,