drm/amd/display: add assert to verify dcn_calc input validity
authorDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Thu, 23 Nov 2017 17:08:13 +0000 (12:08 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 14 Dec 2017 15:57:05 +0000 (10:57 -0500)
This reverts commit 978482d0de86 Revert noisy assert messages

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c

index 453ec1c..47dbc95 100644 (file)
@@ -887,6 +887,17 @@ bool dcn_validate_bandwidth(
                                                + pipe->bottom_pipe->plane_res.scl_data.recout.width;
                        }
 
+                       if (pipe->plane_state->rotation % 2 == 0) {
+                               ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dal_fixed31_32_one.value
+                                       || v->scaler_rec_out_width[input_idx] == v->viewport_width[input_idx]);
+                               ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dal_fixed31_32_one.value
+                                       || v->scaler_recout_height[input_idx] == v->viewport_height[input_idx]);
+                       } else {
+                               ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dal_fixed31_32_one.value
+                                       || v->scaler_recout_height[input_idx] == v->viewport_width[input_idx]);
+                               ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dal_fixed31_32_one.value
+                                       || v->scaler_rec_out_width[input_idx] == v->viewport_height[input_idx]);
+                       }
                        v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no;
                        v->source_pixel_format[input_idx] = tl_pixel_format_to_bw_defs(
                                        pipe->plane_state->format);