arm64/sysreg: Rename TRBSR_EL1 fields per auto-gen tools format

This renames TRBSR_EL1 register fields per auto-gen tools format without
causing any functional change in the TRBE driver.

Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: kvmarm@lists.linux.dev
Cc: coresight@lists.linaro.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20230614065949.146187-5-anshuman.khandual@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 80780de..1df57d6 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -250,19 +250,19 @@
 #define TRBPTR_EL1_PTR_SHIFT           0
 #define TRBBASER_EL1_BASE_MASK         GENMASK_ULL(63, 12)
 #define TRBBASER_EL1_BASE_SHIFT                12
-#define TRBSR_EC_MASK                  GENMASK(5, 0)
-#define TRBSR_EC_SHIFT                 26
-#define TRBSR_IRQ                      BIT(22)
-#define TRBSR_TRG                      BIT(21)
-#define TRBSR_WRAP                     BIT(20)
-#define TRBSR_ABORT                    BIT(18)
-#define TRBSR_STOP                     BIT(17)
-#define TRBSR_MSS_MASK                 GENMASK(15, 0)
-#define TRBSR_MSS_SHIFT                        0
-#define TRBSR_BSC_MASK                 GENMASK(5, 0)
-#define TRBSR_BSC_SHIFT                        0
-#define TRBSR_FSC_MASK                 GENMASK(5, 0)
-#define TRBSR_FSC_SHIFT                        0
+#define TRBSR_EL1_EC_MASK              GENMASK(31, 26)
+#define TRBSR_EL1_EC_SHIFT             26
+#define TRBSR_EL1_IRQ                  BIT(22)
+#define TRBSR_EL1_TRG                  BIT(21)
+#define TRBSR_EL1_WRAP                 BIT(20)
+#define TRBSR_EL1_EA                   BIT(18)
+#define TRBSR_EL1_S                    BIT(17)
+#define TRBSR_EL1_MSS_MASK             GENMASK(15, 0)
+#define TRBSR_EL1_MSS_SHIFT            0
+#define TRBSR_EL1_BSC_MASK             GENMASK(5, 0)
+#define TRBSR_EL1_BSC_SHIFT            0
+#define TRBSR_EL1_FSC_MASK             GENMASK(5, 0)
+#define TRBSR_EL1_FSC_SHIFT            0
 #define TRBMAR_SHARE_MASK              GENMASK(1, 0)
 #define TRBMAR_SHARE_SHIFT             8
 #define TRBMAR_OUTER_MASK              GENMASK(3, 0)

diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
index 1d9d141..1bab91c 100644 (file)
--- a/drivers/hwtracing/coresight/coresight-trbe.c
+++ b/drivers/hwtracing/coresight/coresight-trbe.c
@@ -582,12 +582,12 @@ static void clr_trbe_status(void)
        u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
 
        WARN_ON(is_trbe_enabled());
-       trbsr &= ~TRBSR_IRQ;
-       trbsr &= ~TRBSR_TRG;
-       trbsr &= ~TRBSR_WRAP;
-       trbsr &= ~(TRBSR_EC_MASK << TRBSR_EC_SHIFT);
-       trbsr &= ~(TRBSR_BSC_MASK << TRBSR_BSC_SHIFT);
-       trbsr &= ~TRBSR_STOP;
+       trbsr &= ~TRBSR_EL1_IRQ;
+       trbsr &= ~TRBSR_EL1_TRG;
+       trbsr &= ~TRBSR_EL1_WRAP;
+       trbsr &= ~TRBSR_EL1_EC_MASK;
+       trbsr &= ~TRBSR_EL1_BSC_MASK;
+       trbsr &= ~TRBSR_EL1_S;
        write_sysreg_s(trbsr, SYS_TRBSR_EL1);
 }
 

diff --git a/drivers/hwtracing/coresight/coresight-trbe.h b/drivers/hwtracing/coresight/coresight-trbe.h
index 0b73d9d..3743d90 100644 (file)
--- a/drivers/hwtracing/coresight/coresight-trbe.h
+++ b/drivers/hwtracing/coresight/coresight-trbe.h
@@ -39,7 +39,7 @@ static inline bool is_trbe_enabled(void)
 
 static inline int get_trbe_ec(u64 trbsr)
 {
-       return (trbsr >> TRBSR_EC_SHIFT) & TRBSR_EC_MASK;
+       return (trbsr & TRBSR_EL1_EC_MASK) >> TRBSR_EL1_EC_SHIFT;
 }
 
 #define TRBE_BSC_NOT_STOPPED 0
@@ -48,40 +48,40 @@ static inline int get_trbe_ec(u64 trbsr)
 
 static inline int get_trbe_bsc(u64 trbsr)
 {
-       return (trbsr >> TRBSR_BSC_SHIFT) & TRBSR_BSC_MASK;
+       return (trbsr & TRBSR_EL1_BSC_MASK) >> TRBSR_EL1_BSC_SHIFT;
 }
 
 static inline void clr_trbe_irq(void)
 {
        u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
 
-       trbsr &= ~TRBSR_IRQ;
+       trbsr &= ~TRBSR_EL1_IRQ;
        write_sysreg_s(trbsr, SYS_TRBSR_EL1);
 }
 
 static inline bool is_trbe_irq(u64 trbsr)
 {
-       return trbsr & TRBSR_IRQ;
+       return trbsr & TRBSR_EL1_IRQ;
 }
 
 static inline bool is_trbe_trg(u64 trbsr)
 {
-       return trbsr & TRBSR_TRG;
+       return trbsr & TRBSR_EL1_TRG;
 }
 
 static inline bool is_trbe_wrap(u64 trbsr)
 {
-       return trbsr & TRBSR_WRAP;
+       return trbsr & TRBSR_EL1_WRAP;
 }
 
 static inline bool is_trbe_abort(u64 trbsr)
 {
-       return trbsr & TRBSR_ABORT;
+       return trbsr & TRBSR_EL1_EA;
 }
 
 static inline bool is_trbe_running(u64 trbsr)
 {
-       return !(trbsr & TRBSR_STOP);
+       return !(trbsr & TRBSR_EL1_S);
 }
 
 #define TRBE_TRIG_MODE_STOP            0