aarch64: Enable aarch64_load to use UNSPEC_PRED_X loads

This patch will enable the use of loads using the UNSPEC_PRED_X enum in the
aarch64_load pattern, thus enabling combine to combine such loads with extends.

gcc/ChangeLog:
2021-05-19  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/aarch64/iterators.md (SVE_PRED_LOAD): New iterator.
	(pred_load): New int attribute.
	* config/aarch64/aarch64-sve.md
	(aarch64_load_<ANY_EXTEND:optab><SVE_HSDI:mode><SVE_PARTIAL_I:mode>): Use
	SVE_PRED_LOAD enum iterator and corresponding pred_load attribute.
	* config/aarch64/aarch64-sve-builtins-base.cc (expand): Update call to
	code_for_aarch64_load.

gcc/testsuite/ChangeLog:
2021-05-19  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* gcc.target/aarch64/sve/logical_unpacked_and_2.c: Change
	scan-assembly-times to scan-assembly not for superfluous uxtb.
	* gcc.target/aarch64/sve/logical_unpacked_and_3.c: Likewise.
	* gcc.target/aarch64/sve/logical_unpacked_and_4.c: Likewise.
	* gcc.target/aarch64/sve/logical_unpacked_and_6.c: Likewise.
	* gcc.target/aarch64/sve/logical_unpacked_and_7.c: Likewise.
	* gcc.target/aarch64/sve/logical_unpacked_eor_2.c: Likewise.
	* gcc.target/aarch64/sve/logical_unpacked_eor_3.c: Likewise.
	* gcc.target/aarch64/sve/logical_unpacked_eor_4.c: Likewise.
	* gcc.target/aarch64/sve/logical_unpacked_eor_6.c: Likewise.
	* gcc.target/aarch64/sve/logical_unpacked_eor_7.c: Likewise.
	* gcc.target/aarch64/sve/logical_unpacked_orr_2.c: Likewise.
	* gcc.target/aarch64/sve/logical_unpacked_orr_3.c: Likewise.
	* gcc.target/aarch64/sve/logical_unpacked_orr_4.c: Likewise.
	* gcc.target/aarch64/sve/logical_unpacked_orr_6.c: Likewise.
	* gcc.target/aarch64/sve/logical_unpacked_orr_7.c: Likewise.
	* gcc.target/aarch64/sve/ld1_extend.c: New test.

diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
index dfdf0e2..8fd6d3f 100644 (file)
--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
@@ -1123,7 +1123,7 @@ public:
   rtx
   expand (function_expander &e) const OVERRIDE
   {
-    insn_code icode = code_for_aarch64_load (extend_rtx_code (),
+    insn_code icode = code_for_aarch64_load (UNSPEC_LD1_SVE, extend_rtx_code (),
                                             e.vector_mode (0),
                                             e.memory_vector_mode ());
     return e.use_contiguous_load_insn (icode);

diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index b8b6f55..9e48c0e 100644 (file)
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -1287,7 +1287,7 @@
 ;; -------------------------------------------------------------------------
 
 ;; Predicated load and extend, with 8 elements per 128-bit block.
-(define_insn_and_rewrite "@aarch64_load_<ANY_EXTEND:optab><SVE_HSDI:mode><SVE_PARTIAL_I:mode>"
+(define_insn_and_rewrite "@aarch64_load<SVE_PRED_LOAD:pred_load>_<ANY_EXTEND:optab><SVE_HSDI:mode><SVE_PARTIAL_I:mode>"
   [(set (match_operand:SVE_HSDI 0 "register_operand" "=w")
        (unspec:SVE_HSDI
          [(match_operand:<SVE_HSDI:VPRED> 3 "general_operand" "UplDnm")
@@ -1295,7 +1295,7 @@
             (unspec:SVE_PARTIAL_I
               [(match_operand:<SVE_PARTIAL_I:VPRED> 2 "register_operand" "Upl")
                (match_operand:SVE_PARTIAL_I 1 "memory_operand" "m")]
-              UNSPEC_LD1_SVE))]
+              SVE_PRED_LOAD))]
          UNSPEC_PRED_X))]
   "TARGET_SVE && (~<SVE_HSDI:narrower_mask> & <SVE_PARTIAL_I:self_mask>) == 0"
   "ld1<ANY_EXTEND:s><SVE_PARTIAL_I:Vesize>\t%0.<SVE_HSDI:Vctype>, %2/z, %1"

diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 69d9dbe..f133bfd 100644 (file)
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -2516,6 +2516,10 @@
 
 (define_int_iterator SVE_LDFF1_LDNF1 [UNSPEC_LDFF1 UNSPEC_LDNF1])
 
+(define_int_iterator SVE_PRED_LOAD [UNSPEC_PRED_X UNSPEC_LD1_SVE])
+
+(define_int_attr pred_load [(UNSPEC_PRED_X "_x") (UNSPEC_LD1_SVE "")])
+
 (define_int_iterator SVE2_U32_UNARY [UNSPEC_URECPE UNSPEC_RSQRTE])
 
 (define_int_iterator SVE2_INT_UNARY_NARROWB [UNSPEC_SQXTNB

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/ld1_extend.c b/gcc/testsuite/gcc.target/aarch64/sve/ld1_extend.c
new file mode 100644 (file)
index 0000000..7f78cb4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/ld1_extend.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 --param vect-partial-vector-usage=1" } */
+
+void foo (signed char * __restrict__ a, signed char * __restrict__ b, short * __restrict__ c, int n)
+{
+    for (int i = 0; i < n; ++i)
+      c[i] = a[i] + b[i];
+}
+
+/* { dg-final { scan-assembler-times {\tld1sb\t} 4 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_2.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_2.c
index 08b2745..505767a 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_2.c
@@ -11,7 +11,7 @@ f (uint64_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2)
 
 /* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
-/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.h,} 1 } } */
+/* { dg-final { scan-assembler-not {\tuxtb\tz[0-9]+\.h,} } } */
 /* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_3.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_3.c
index c823470..f7d4360 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_3.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_3.c
@@ -11,7 +11,7 @@ f (uint64_t *restrict dst, uint32_t *restrict src1, uint8_t *restrict src2)
 
 /* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
-/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-not {\tuxtb\tz[0-9]+\.s,} } } */
 /* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_4.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_4.c
index 52c9291..1aef903 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_4.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_4.c
@@ -11,7 +11,7 @@ f (uint64_t *restrict dst, uint32_t *restrict src1, uint16_t *restrict src2)
 
 /* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */
-/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-not {\tuxth\tz[0-9]+\.s,} } } */
 /* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_6.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_6.c
index 1552ed8..fb58b52 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_6.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_6.c
@@ -11,7 +11,7 @@ f (uint64_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2)
 
 /* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
-/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.h,} 1 } } */
+/* { dg-final { scan-assembler-not {\tuxtb\tz[0-9]+\.h,} } } */
 /* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */
 /* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_7.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_7.c
index 484d9da..34b2cc0 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_7.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_and_7.c
@@ -10,7 +10,7 @@ f (uint64_t *restrict dst, uint32_t *restrict src1, uint8_t *restrict src2){
 
 /* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
-/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-not {\tuxtb\tz[0-9]+\.s,} } } */
 /* { dg-final { scan-assembler-times {\tand\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */
 /* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_2.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_2.c
index 23ddeb9..529c073 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_2.c
@@ -11,7 +11,7 @@ f (uint64_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2)
 
 /* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
-/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.h,} 1 } } */
+/* { dg-final { scan-assembler-not {\tuxtb\tz[0-9]+\.h,} } } */
 /* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_3.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_3.c
index 4dd1e08..b6b0119 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_3.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_3.c
@@ -11,7 +11,7 @@ f (uint64_t *restrict dst, uint32_t *restrict src1, uint8_t *restrict src2)
 
 /* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
-/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-not {\tuxtb\tz[0-9]+\.s,} } } */
 /* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_4.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_4.c
index a31a2d4..a61eed4 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_4.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_4.c
@@ -11,7 +11,7 @@ f (uint64_t *restrict dst, uint32_t *restrict src1, uint16_t *restrict src2)
 
 /* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */
-/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-not {\tuxth\tz[0-9]+\.s,} } } */
 /* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_6.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_6.c
index 416567b..a3fde4b 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_6.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_6.c
@@ -11,7 +11,7 @@ f (uint64_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2)
 
 /* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
-/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.h,} 1 } } */
+/* { dg-final { scan-assembler-not {\tuxtb\tz[0-9]+\.h,} } } */
 /* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */
 /* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_7.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_7.c
index 3f7c3dd..8e01f3f 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_7.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_eor_7.c
@@ -10,7 +10,7 @@ f (uint64_t *restrict dst, uint32_t *restrict src1, uint8_t *restrict src2){
 
 /* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
-/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-not {\tuxtb\tz[0-9]+\.s,} } } */
 /* { dg-final { scan-assembler-times {\teor\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */
 /* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_2.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_2.c
index 593de65..763c81b 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_2.c
@@ -11,7 +11,7 @@ f (uint64_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2)
 
 /* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
-/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.h,} 1 } } */
+/* { dg-final { scan-assembler-not {\tuxtb\tz[0-9]+\.h,} } } */
 /* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_3.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_3.c
index ec34e75..17fddcd 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_3.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_3.c
@@ -11,7 +11,7 @@ f (uint64_t *restrict dst, uint32_t *restrict src1, uint8_t *restrict src2)
 
 /* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
-/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-not {\tuxtb\tz[0-9]+\.s,} } } */
 /* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_4.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_4.c
index 561a104..4e8c4d0 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_4.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_4.c
@@ -11,7 +11,7 @@ f (uint64_t *restrict dst, uint32_t *restrict src1, uint16_t *restrict src2)
 
 /* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */
-/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-not {\tuxth\tz[0-9]+\.s,} } } */
 /* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_6.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_6.c
index 3ce1c3f..26103cf 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_6.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_6.c
@@ -11,7 +11,7 @@ f (uint64_t *restrict dst, uint16_t *restrict src1, uint8_t *restrict src2)
 
 /* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
-/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.h,} 1 } } */
+/* { dg-final { scan-assembler-not {\tuxtb\tz[0-9]+\.h,} } } */
 /* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */
 /* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_7.c b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_7.c
index e6a4291..06e1b58 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_7.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/logical_unpacked_orr_7.c
@@ -10,7 +10,7 @@ f (uint64_t *restrict dst, uint32_t *restrict src1, uint8_t *restrict src2){
 
 /* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 2 } } */
-/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.s,} 1 } } */
+/* { dg-final { scan-assembler-not {\tuxtb\tz[0-9]+\.s,} } } */
 /* { dg-final { scan-assembler-times {\torr\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */
 /* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 2 } } */
 /* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d,} 2 } } */