[X86][MMX] Remove widening experimental flag from MMX tests.

Turns out that after the past MMX commits, we don't need to rely on this
flag to get better codegen for MMX. Also update the tests to become
triple neutral.

llvm-svn: 230637

diff --git a/llvm/test/CodeGen/X86/bitcast-mmx.ll b/llvm/test/CodeGen/X86/bitcast-mmx.ll
index 0f2c21a..8aeee1d 100644 (file)
--- a/llvm/test/CodeGen/X86/bitcast-mmx.ll
+++ b/llvm/test/CodeGen/X86/bitcast-mmx.ll
@@ -1,9 +1,9 @@
-; RUN: llc < %s -mtriple=x86_64-darwin -x86-experimental-vector-widening-legalization -mattr=+mmx,+sse2 | FileCheck %s
+; RUN: llc < %s -march=x86_64 -mattr=+mmx,+sse2 | FileCheck %s
 
 define i32 @t0(i64 %x) {
 ; CHECK-LABEL: t0:
-; CHECK:       ## BB#0: ## %entry
-; CHECK-NEXT:    movd %rdi, %mm0
+; CHECK:       # BB#0:{{.*}} %entry
+; CHECK:    movd %[[REG1:[a-z]+]], %mm0
 ; CHECK-NEXT:    pshufw $238, %mm0, %mm0
 ; CHECK-NEXT:    movd %mm0, %eax
 ; CHECK-NEXT:    retq
@@ -21,9 +21,9 @@ entry:
 
 define i64 @t1(i64 %x, i32 %n) {
 ; CHECK-LABEL: t1:
-; CHECK:       ## BB#0: ## %entry
-; CHECK-NEXT:    movd %esi, %mm0
-; CHECK-NEXT:    movd %rdi, %mm1
+; CHECK:       # BB#0:{{.*}} %entry
+; CHECK:    movd %[[REG2:[a-z]+]], %mm0
+; CHECK-NEXT:    movd %[[REG1]], %mm1
 ; CHECK-NEXT:    psllq %mm0, %mm1
 ; CHECK-NEXT:    movd %mm1, %rax
 ; CHECK-NEXT:    retq
@@ -36,14 +36,14 @@ entry:
 
 define i64 @t2(i64 %x, i32 %n, i32 %w) {
 ; CHECK-LABEL: t2:
-; CHECK:       ## BB#0: ## %entry
-; CHECK-NEXT:    movd %esi, %mm0
-; CHECK-NEXT:    movd %edx, %mm1
-; CHECK-NEXT:    psllq %mm0, %mm1
-; CHECK-NEXT:    movd %rdi, %mm0
-; CHECK-NEXT:    por %mm1, %mm0
-; CHECK-NEXT:    movd %mm0, %rax
-; CHECK-NEXT:    retq
+; CHECK:       # BB#0:{{.*}} %entry
+; CHECK:  movd %[[REG4:[a-z]+]], %mm0
+; CHECK-NEXT:  movd %[[REG6:[a-z0-9]+]], %mm1
+; CHECK-NEXT:  psllq %mm0, %mm1
+; CHECK-NEXT:  movd %[[REG1]], %mm0
+; CHECK-NEXT:  por %mm1, %mm0
+; CHECK-NEXT:  movd %mm0, %rax
+; CHECK-NEXT:  retq
 entry:
   %0 = insertelement <2 x i32> undef, i32 %w, i32 0
   %1 = insertelement <2 x i32> %0, i32 0, i32 1
@@ -57,9 +57,9 @@ entry:
 
 define i64 @t3(<1 x i64>* %y, i32* %n) {
 ; CHECK-LABEL: t3:
-; CHECK:       ## BB#0: ## %entry
-; CHECK-NEXT:    movq (%rdi), %mm0
-; CHECK-NEXT:    psllq (%rsi), %mm0
+; CHECK:       # BB#0:{{.*}} %entry
+; CHECK:    movq (%[[REG1]]), %mm0
+; CHECK-NEXT:    psllq (%[[REG3:[a-z]+]]), %mm0
 ; CHECK-NEXT:    movd %mm0, %rax
 ; CHECK-NEXT:    retq
 entry:

diff --git a/llvm/test/CodeGen/X86/vec_extract-mmx.ll b/llvm/test/CodeGen/X86/vec_extract-mmx.ll
index 6b467b8..118163c 100644 (file)
--- a/llvm/test/CodeGen/X86/vec_extract-mmx.ll
+++ b/llvm/test/CodeGen/X86/vec_extract-mmx.ll
@@ -1,12 +1,13 @@
-; RUN: llc < %s -mtriple=x86_64-darwin -x86-experimental-vector-widening-legalization -mattr=+mmx,+sse2 | FileCheck %s
+; RUN: llc < %s -march=x86_64 -mattr=+mmx,+sse2 | FileCheck %s
 
 define i32 @test0(<1 x i64>* %v4) {
 ; CHECK-LABEL: test0:
-; CHECK:       ## BB#0:
-; CHECK-NEXT:    pshufw $238, (%rdi), %mm0
+; CHECK:       # BB#0:{{.*}} %entry
+; CHECK:    pshufw $238, (%[[REG:[a-z]+]]), %mm0
 ; CHECK-NEXT:    movd %mm0, %eax
 ; CHECK-NEXT:    addl $32, %eax
 ; CHECK-NEXT:    retq
+entry:
   %v5 = load <1 x i64>* %v4, align 8
   %v12 = bitcast <1 x i64> %v5 to <4 x i16>
   %v13 = bitcast <4 x i16> %v12 to x86_mmx
@@ -22,8 +23,8 @@ define i32 @test0(<1 x i64>* %v4) {
 
 define i32 @test1(i32* nocapture readonly %ptr) {
 ; CHECK-LABEL: test1:
-; CHECK:       ## BB#0: ## %entry
-; CHECK-NEXT:    movd (%rdi), %mm0
+; CHECK:       # BB#0:{{.*}} %entry
+; CHECK:    movd (%[[REG]]), %mm0
 ; CHECK-NEXT:    pshufw $232, %mm0, %mm0
 ; CHECK-NEXT:    movd %mm0, %eax
 ; CHECK-NEXT:    emms
@@ -48,8 +49,8 @@ entry:
 
 define i32 @test2(i32* nocapture readonly %ptr) {
 ; CHECK-LABEL: test2:
-; CHECK:       ## BB#0: ## %entry
-; CHECK-NEXT:    pshufw $232, (%rdi), %mm0
+; CHECK:       # BB#0:{{.*}} %entry
+; CHECK:    pshufw $232, (%[[REG]]), %mm0
 ; CHECK-NEXT:    movd %mm0, %eax
 ; CHECK-NEXT:    emms
 ; CHECK-NEXT:    retq