BZ: 24239
currently USB OTG in clv doesn't have d1_supported flag set in pci
pm cap register. Same as mfld, mid_pmu driver uses PCI_D1 for pci
power states transition, and need this quirk until we got pm cap
fixed in fw.
Change-Id: I07a5d63a02386d92c06c926d4f65a9a0f62408c9
Signed-off-by: Wu, Hao <hao.wu@intel.com>
Reviewed-on: http://android.intel.com:8080/36829
Reviewed-by: Meng, Zhe <zhe.meng@intel.com>
Tested-by: Meng, Zhe <zhe.meng@intel.com>
Reviewed-by: Tang, Richard <richard.tang@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>
#ifdef CONFIG_USB_PENWELL_OTG
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0829, quirk_mfld_d1_support);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xE006, quirk_mfld_d1_support);
#endif /*CONFIG_USB_PENWELL_OTG*/
#ifdef CONFIG_SERIAL_MFD_HSU